| 2022 | ITC | Industry Evaluation of Reversible Scan Chain Diagnosis. | Soumya Mittal, Szczepan Urban, Kun Young Chung, Jakub Janicki, Wu-Tung Cheng, Martin Parley, Manish Sharma, Shaun Nicholson |
| 2017 | VTS | Innovative practices session 9C DFT and data for diagnostics. | Kun Young Chung, Stefano Di Carlo |
| 2016 | ASPDAC | Learning-based prediction of embedded memory timing failures during initial floorplan design. | Wei-Ting Jonas Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath |
| 2016 | DAC | Comprehensive optimization of scan chain timing during late-stage IC implementation. | Kun Young Chung, Andrew B. Kahng, Jiajia Li |
| 2013 | VTS | Innovative practices session 6C: Latest practices in test compression. | Jonathon E. Colburn, Kun Young Chung, Haluk Konuk, Y. Dong |
| 2010 | ITC | Design and test of latch-based circuits to maximize performance, yield, and delay test quality. | Kun Young Chung, Sandeep K. Gupta |
| 2009 | VTS | Efficient Scheduling of Path Delay Tests for Latch-Based Circuits. | Kun Young Chung, Sandeep K. Gupta |
| 2006 | VTS | Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing. | Kun Young Chung, Sandeep K. Gupta |
| 2003 | ITC | Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing. | Kun Young Chung, Sandeep K. Gupta |