| 2004 | ISCAS | Graphics processor unit (GPU) acceleration of finite-difference time-domain (FDTD) algorithm. | Sean E. Krakiwsky, Laurence E. Turner, Michal M. Okoniewski |
| 2002 | FPGA | Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method. | Ryan N. Schneider, Laurence E. Turner, Michal M. Okoniewski |
| 2002 | FPL | A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits | Alex Carreira, Trevor W. Fox, Laurence E. Turner |
| 2002 | FPL | Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. | Trevor W. Fox, Laurence E. Turner |
| 2002 | ISCAS | Low coefficient complexity approximations of the one dimensional discrete cosine transform. | Trevor W. Fox, Laurence E. Turner |
| 2001 | ISCAS | The design of peak constrained least squares FIR filters with low complexity finite precision coefficients. | Trevor W. Fox, Laurence E. Turner |
| 1997 | FPL | An FPGA implementation of a matched filter detector for spread spectrum communications systems. | T. Mathews, S. G. Gibb, Laurence E. Turner, Peter J. W. Graumann, Michel Fattouche |
| 1995 | FPL | Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs. | Gopal Panneerselvam, Peter J. W. Graumann, Laurence E. Turner |
| 1995 | FPL | Rapid Hardware Prototyping of Digital Signal Processing Systems Using FPGAs. | Laurence E. Turner, Peter J. W. Graumann |
| 1995 | FPL | BIT-Serial FIR Filters with CSD Coefficients for FPGAs. | Laurence E. Turner, Peter J. W. Graumann, S. G. Gibb |
| 1994 | ISCAS | DSP System Synthesis Including Variable Data Path Width. | Bruce A. Johnston, Peter J. W. Graumann, Laurence E. Turner |
| 1993 | ISCAS | A method of evaluating the effects of signal quantization at arbitrary locations in recursive digital filters. | Stephen Worthington, Laurence E. Turner |
| 1984 | ICASSP | A bit serial LDI recursive digital filter. | Laurence E. Turner, Peter B. Denyer, David Renshaw |