| 2025 | ASPDAC | GSNorm: An Efficient 3D Gaussian Rendering Accelerator with Splat Normalization and LUT-assist Rasterization. | Yiyang Sun, Peiran Yan, Yiqi Jing, Le Ye, Tianyu Jia |
| 2025 | CVPR | Accelerating Diffusion Transformer via Increment-Calibrated Caching with Channel-Aware Singular Value Decomposition. | Zhiyuan Chen, Keyi Li, Yifan Jia, Le Ye, Yufei Ma |
| 2025 | DAC | EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at Edge. | Kangbo Bai, Le Ye, Ru Huang, Tianyu Jia |
| 2025 | DAC | 3D-SubG: A 3D Stacked Hybrid Processing Near/In-Memory Accelerator for Subgraph GNNs. | Guoxiang Li, Runnan Xu, Ruohang Xu, Yikan Qiu, Renati Tuerhong, Muhan Zhang, Le Ye, Yufei Ma |
| 2025 | DAC | Local-GS: An Order-Independent Gaussian Splatting Training Accelerator Exploiting Splat Locality. | Yiyang Sun, Qinzhe Zhi, Yiqi Jing, Le Ye, Ru Huang, Tianyu Jia |
| 2025 | DAC | 3D-TokSIM: Stacking 3D Memory with Token-Stationary Compute-in-Memory for Speculative LLM Inference. | Wentao Zhao, Boya Lv, Meng Wu, Peiyu Chen, Fengyun Yan, Yufei Ma, Tianyu Jia, Ru Huang, Le Ye |
| 2025 | DATE | Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs. | Zhantong Zhu, Hongou Li, Wenjie Ren, Meng Wu, Le Ye, Ru Huang, Tianyu Jia |
| 2025 | ICCAD | H | Zizhuo Fu, Xiaotian Guo, Wenxuan Zeng, Shuzhang Zhong, Yadong Zhang, Peiyu Chen, Runsheng Wang, Le Ye, Meng Li |
| 2025 | ICCAD | CIMTester: An Agile Golden-Result-Free BIST Compiler for Robust Compute-In-Memory. | Wenjie Ren, Meng Wu, Mingxuan Li, Peiyu Chen, Tianyu Jia, Le Ye |
| 2025 | ISCAS | A 22nm All-digital Fully Synthesizable Adaptive Clock Generator for Fast Frequency Adjustment in AI Processor. | Xueping Liu, Le Ye, Tianyu Jia |
| 2024 | DAC | An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology. | Zhiyuan Chen, Yufei Ma, Keyi Li, Yifan Jia, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang |
| 2024 | DAC | AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration. | Yiqi Jing, Meng Wu, Jiaqi Zhou, Yiyang Sun, Yufei Ma, Ru Huang, Tianyu Jia, Le Ye |
| 2024 | DAC | SPARK: An Efficient Hybrid Acceleration Architecture with Run-Time Sparsity-Aware Scheduling for TinyML Learning. | Mingxuan Li, Qinzhe Zhi, Yanchi Dong, Le Ye, Tianyu Jia |
| 2024 | ICCAD | Hierarchical Power Co-Optimization and Management for LLM Chiplet Designs. | Yanchi Dong, Xueping Liu, Xiaochen Hao, Yun Liang, Ru Huang, Le Ye, Tianyu Jia |
| 2023 | ASPDAC | RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation. | Peiyu Chen, Meng Wu, Yufei Ma, Le Ye, Ru Huang |
| 2023 | DAC | A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware. | Yanchi Dong, Tianyu Jia, Kaixuan Du, Yiqi Jing, Qijun Wang, Pixian Zhan, Yadong Zhang, Fengyun Yan, Yufei Ma, Yun Liang, Le Ye, Ru Huang |
| 2023 | ICCAD | ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions. | Xiuping Cui, Size Zheng, Tianyu Jia, Le Ye, Yun Liang |
| 2023 | ISCAS | An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications. | Yiqi Jing, Zhixuan Wang, Linxiao Shen, Yihan Zhang, Peiyu Chen, Jiayoon Ru, Le Ye |
| 2023 | ISLPED | DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler. | Yiqi Jing, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu, Fengyun Yan, Yufei Ma, Le Ye, Tianyu Jia |
| 2022 | ICCAD | DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks. | Yikan Qiu, Yufei Ma, Wentao Zhao, Meng Wu, Le Ye, Ru Huang |
| 2022 | ISCAS | Reliability-Improved Read Circuit and Self-Terminating Write Circuit for STT-MRAM in 16 nm FinFET. | Chang Xue, Yihan Zhang, Peiyu Chen, Mingwei Zhu, Tianqiao Wu, Meng Wu, Yandong He, Le Ye |
| 2022 | ISCAS | A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique. | Xinhang Xu, Siyuan Ye, Jihang Gao, Yihan Zhang, Linxiao Shen, Le Ye |
| 2021 | FPGA | SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA. | Yufei Ma, Gokul Krishnan, Yu Cao, Le Ye, Ru Huang |
| 2020 | ISCAS | A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection. | Xiaolong Chen, Enbin Gong, Hao Zhang, Le Ye, Ru Huang |
| 2020 | ISCAS | 2.4-GHz 16-QAM Passive Backscatter Transmitter for Wireless Self-Power Chips in IoT. | Enbin Gong, Hao Zhang, Xiaolong Chen, Le Ye, Ru Huang |
| 2019 | ISCAS | Ultra-Low Power Hybrid TFET-MOSFET Topologies for Standard Logic Cells with Improved Comprehensive Performance. | Zhixuan Wang, Yuan Zhong, Cheng Chen, Le Ye, Qianqian Huang, Libo Yang, Yangyuan Wang, Ru Huang |
| 2018 | ISCAS | Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications. | Libo Yang, Jiadi Zhu, Cheng Chen, Zhixuan Wang, Zexue Liu, Qianqian Huang, Le Ye, Ru Huang |
| 2017 | ISCAS | Benchmarking TFET from a circuit level perspective: Applications and guideline. | Lingyi Guo, Le Ye, Cheng Chen, Qianqian Huang, Libo Yang, Zhu Lv, Xia An, Ru Huang |
| 2014 | ISCAS | A UHF RFID reader transmitter with digital CMOS power amplifier. | Ying Guo, Long Chen, Tao Xia, Le Ye, Xing Zhang, Huailin Liao |
| 2013 | ISCAS | SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter. | Yongan Zheng, Le Ye, Long Chen, Huailin Liao, Ru Huang |
| 2012 | ISCAS | A +21.2 dBm out-of-band IIP3 0.2-3GHz RF front-end using impedance translation technique. | Long Chen, Chuan Wang, Chen Li, Le Ye, Huailin Liao, Ru Huang |
| 2012 | ISCAS | Cost-efficient CMOS RF tunable bandpass filter with active inductor-less biquads. | Yixiao Wang, Le Ye, Huailin Liao, Ru Huang |
| 2012 | ISCAS | Widely reconfigurable 8 | Le Ye, Yixiao Wang, Long Chen, Huailin Liao, Ru Huang |
| 2011 | ISCAS | -99dBc/Hz@10kHz 1MHz-step dual-loop integer-N PLL with anti-mislocking frequency calibration for global navigation satellite system receiver. | Congyin Shi, Chuan Wang, Le Ye, Huailin Liao |
| 2011 | ISCAS | A 0.47mW 6 | Le Ye, Congyin Shi, Huailin Liao, Ru Huang |