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Liang-Chi Chen

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

15

Venues

8

Active years

1993–2026

Best venue rank

A*

Where they publish

Papers

15 indexed papers, newest first.

YearVenueTitleAuthors
2026DATELAMP: An Adaptive Near-Memory Processing System for High-Performance Long-Read Mapping.Jo-Ling Huang, Liang-Chi Chen, Chien-Chung Ho, Yuan-Hao Chang
2026SACAccelerating RNA-Seq Pseudoalignment via NAND Flash-based In-Memory-Searching Architecture.Guan-De Jiang, Ying-Sheng Huang, Liang-Chi Chen, Chien-Chung Ho
2025DACPIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System.Chun-Le Yeh, Liang-Chi Chen, Chien-Chung Ho, Yu-Ming Chang, Da-Wei Chang
2025ISLPEDAridWalk: Efficient Graph Random Walks on a Resource-Limited Computational Storage Device.Liang-Chi Chen, Chien-Chung Ho, Tei-Wei Kuo, Yuan-Hao Chang
2023DACUpPipe: A Novel Pipeline Management on In-Memory Processors for RNA-seq Quantification.Liang-Chi Chen, Chien-Chung Ho, Yuan-Hao Chang
2023SACEfficient Sanitization Design for LSM-based Key-Value Store over 3D MLC NAND Flash.Liang-Chi Chen, Shu-Qi Yu, Chien-Chung Ho, Wei-Chen Wang, Yung-Chun Li
2020HCIApplying Holo360 Video and Image Super-Resolution Generative Adversarial Networks to Virtual Reality Immersion.Chia-Hui Feng, Yu-Hsiu Hung, Chao-Kuang Yang, Liang-Chi Chen, Wen-Cheng Hsu, Shih-Hao Lin
2020HCIResearch on Aesthetic Perception of Artificial Intelligence Style Transfer.Chia-Hui Feng, Yu-Chun Lin, Yu-Hsiu Hung, Chao-Kuang Yang, Liang-Chi Chen, Shih-Wei Yeh, Shih-Hao Lin
2011ITCTransition test bring-up and diagnosis on UltraSPARCLiang-Chi Chen, Peter Dahlgren, Paul Dickinson, Scott Davidson
2009ITCUsing transition test to understand timing behavior of logic circuits on UltraSPARCLiang-Chi Chen, Paul Dickinson, Peter Dahlgren, Scott Davidson, Olivier Caty, Kevin Wu
2008ITCTransition Test on UltraSPARC- T2 Microprocessor.Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen
2001DACA New Gate Delay Model for Simultaneous Switching and Its Applications.Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
2001ITCCrosstalk test generation on pseudo industrial circuits: a case study.Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer
1997VTSHigh Quality Robust Tests for Path Delay Faults.Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer
1993ICCADOn-chip test generation for combinational circuits by LFSR modification.Shambhu J. Upadhyaya, Liang-Chi Chen