Luca Gaetano Amar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
28
Venues
7
Active years
2013–2021
Best venue rank
A*
Where they publish
Papers
28 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | DAC | LUT-Based Optimization For ASIC Design Flow. | Luca Gaetano Amar, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli |
| 2018 | DATE | Improvements to boolean resynthesis. | Luca Gaetano Amar, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli |
| 2018 | DATE | Practical exact synthesis. | Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amar, Robert K. Brayton, Giovanni De Micheli |
| 2017 | ASPDAC | Multi-level logic benchmarks: An exactness study. | Luca Gaetano Amar, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2017 | ASPDAC | A novel basis for logic rewriting. | Winston Haaswijk, Mathias Soeken, Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2017 | DATE | Logic optimization and synthesis: Trends and directions in industry. | Luca Gaetano Amar, Patrick Vuillod, Jiong Luo, Janet Olson |
| 2017 | DATE | Wave pipelining for majority-based beyond-CMOS technologies. | Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amar, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins |
| 2017 | ICCAD | Enabling exact delay synthesis. | Luca Gaetano Amar, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli |
| 2016 | ASPDAC | Majority-based synthesis for nanotechnologies. | Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2016 | DAC | An MIG-based compiler for programmable logic-in-memory architectures. | Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amar, Rolf Drechsler, Giovanni De Micheli |
| 2016 | DATE | Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking. | Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli |
| 2016 | DATE | The Programmable Logic-in-Memory (PLiM) computer. | Pierre-Emmanuel Gaillardon, Luca Gaetano Amar, Anne Siemon, Eike Linn, Rainer Waser, Anupam Chattopadhyay, Giovanni De Micheli |
| 2016 | DATE | Optimizing Majority-Inverter Graphs with functional hashing. | Mathias Soeken, Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2016 | ISCAS | Digital, analog and RF design opportunities of three-independent-gate transistors. | Pierre-Emmanuel Gaillardon, Mehdi Hasan, Anirban Saha, Luca Gaetano Amar, Ross Walker, Berardi Sensale Rodriguez |
| 2015 | ASPDAC | Multiple Independent Gate FETs: How many gates do we need? | Luca Gaetano Amar, Gage Hills, Pierre-Emmanuel Gaillardon, Subhasish Mitra, Giovanni De Micheli |
| 2015 | FPGA | Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only). | Pierre-Emmanuel Gaillardon, Gain Kim, Xifan Tang, Luca Gaetano Amar, Giovanni De Micheli |
| 2014 | ASPDAC | Data compression via logic synthesis. | Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Andreas Burg, Giovanni De Micheli |
| 2014 | DAC | Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization. | Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2014 | DATE | An efficient manipulation package for Biconditional Binary Decision Diagrams. | Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2014 | DATE | Advanced system on a chip design based on controllable-polarity FETs. | Pierre-Emmanuel Gaillardon, Luca Gaetano Amar, Jian Zhang, Giovanni De Micheli |
| 2014 | DSD | Majority Logic Synthesis for Spin Wave Technology. | Odysseas Zografos, Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Praveen Raghavan, Giovanni De Micheli |
| 2014 | FPGA | A new basic logic structure for data-path computation (abstract only). | Pierre-Emmanuel Gaillardon, Luca Gaetano Amar, Giovanni De Micheli |
| 2013 | ASPDAC | MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits. | Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2013 | DAC | BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition. | Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2013 | DAC | Towards structured ASICs using polarity-tunable Si nanowire transistors. | Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amar, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli |
| 2013 | DATE | Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits. | Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2013 | DATE | Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. | Pierre-Emmanuel Gaillardon, Luca Gaetano Amar, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli |
| 2013 | ISCAS | Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET. | Ogun Turkyilmaz, Fabien Clermidy, Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |