| 2018 | DSD | Memory Aware Packet Matching Architecture for High-Speed Networks. | Michal Kekely, Lukas Kekely, Jan Korenek |
| 2018 | FPGA | Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. | Jakub Cabal, Pavel Bencek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek |
| 2018 | FPL | Accelerated Wire-Speed Packet Capture at 200 Gbps. | Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek |
| 2018 | ICCD | General IDS Acceleration for High-Speed Networks. | Jan Kucera, Lukas Kekely, Adam Piecek, Jan Korenek |
| 2018 | NOMS | Live demonstration of FPGA based networking accelerator for 200 Gbps data transfers. | Lukas Kekely, Martin Spinler, Stepan Friedl, Jiri Sikora, Jan Korenek |
| 2015 | IM | Hardware accelerated flow measurement of 100 Gb ethernet. | Viktor Pus, Petr Velan, Lukas Kekely, Jan Korenek, Pavel Minark |
| 2014 | DDECS | Fast lookup for dynamic packet filtering in FPGA. | Lukas Kekely, Martin Zdnk, Jir Matousek, Jan Korenek |
| 2014 | DDECS | Design methodology of configurable high performance packet parser for FPGA. | Viktor Pus, Lukas Kekely, Jan Korenek |
| 2014 | DDECS | CRC based hashing in FPGA using DSP blocks. | Toms Zvodnk, Lukas Kekely, Viktor Pus |
| 2014 | FPGA | Using DSP blocks to compute CRC hash in FPGA (abstract only). | Viktor Pus, Lukas Kekely, Toms Zvodnk |
| 2014 | FPL | Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. | Lukas Kekely, Viktor Pus, Pavel Bencek, Jan Korenek |
| 2014 | INFOCOM | Software Defined Monitoring of application protocols. | Lukas Kekely, Viktor Pus, Jan Korenek |