Madhu K. Iyer
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
11
Venues
6
Active years
1998–2005
Best venue rank
A*
Where they publish
Papers
11 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | DAC | Structural search for RTL with predicate learning. | Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer |
| 2005 | DATE | Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. | Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng |
| 2005 | DATE | An Efficient Sequential SAT Solver With Improved Search Strategies. | Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen |
| 2005 | ICCAD | RTL SAT simplification by Boolean and interval arithmetic reasoning. | Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer |
| 2004 | ASPDAC | Efficient reachability checking using sequential SAT. | Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang |
| 2004 | DAC | An efficient finite-domain constraint solver for circuits. | Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang |
| 2003 | ICCAD | SATORI - A Fast Sequential SAT Engine for Circuits. | Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng |
| 2002 | ITC | Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. | Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir |
| 2002 | VTS | Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs. | Madhu K. Iyer, Kwang-Ting Cheng |
| 2001 | VTS | A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. | Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng |
| 1998 | VTS | Effect of Noise on Analog Circuit Testing. | Madhu K. Iyer, Michael L. Bushnell |