Mahyar Emami
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
4
Active years
2020–2025
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ASPLOS | Parendi: Thousand-Way Parallel RTL Simulation. | Mahyar Emami, Thomas Bourgeat, James R. Larus |
| 2024 | FPGA | A 475 MHz Manycore FPGA Accelerator for RTL Simulation. | Sahand Kashani, Mahyar Emami, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus |
| 2024 | OSDI | Performance Interfaces for Hardware Accelerators. | Jiacheng Ma, Rishabh R. Iyer, Sahand Kashani, Mahyar Emami, Thomas Bourgeat, George Candea |
| 2023 | ASPLOS | Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism. | Mahyar Emami, Sahand Kashani, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus |
| 2022 | FPL | Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats. | Sahand Kashani, Mahyar Emami, James R. Larus |
| 2021 | FPGA | Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems. | Mahyar Emami, Endri Bezati, Jrn W. Janneck, James R. Larus |
| 2020 | FPGA | Advanced Dataflow Programming using Actor Machines for High-Level Synthesis. | Endri Bezati, Mahyar Emami, James R. Larus |