Manish Kumar Jaiswal
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
5
Active years
2009–2018
Best venue rank
A
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | DATE | Universal number posit arithmetic generator on FPGA. | Manish Kumar Jaiswal, Hayden Kwok-Hay So |
| 2018 | ISCAS | Architecture Generator for Type-3 Unum Posit Adder/Subtractor. | Manish Kumar Jaiswal, Hayden Kwok-Hay So |
| 2013 | FPL | Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM). | Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung |
| 2012 | FCCM | Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers. | Manish Kumar Jaiswal, Ray C. C. Cheung |
| 2009 | VLSID | Efficient Implementation of Floating-Point Reciprocator on FPGA. | Manish Kumar Jaiswal, Nitin Chandrachoodan |