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Manuel E. Acacio

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

50

Venues

18

Active years

1999–2026

Best venue rank

A*

Where they publish

Papers

50 indexed papers, newest first.

YearVenueTitleAuthors
2026HPCAQuCo: Efficient and Flexible Hardware-Driven Automatic Configuration of Tile Transfers in GPUs.Nicols Meseguer, Daoxuan Xu, Yifan Sun, Michael Pellauer, Jos L. Abelln, Manuel E. Acacio
2025HPCANo Rush in Executing Atomic Instructions.Ashkan Asgharzadeh, Josu Feliu, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros
2025ICCDQuFi: Adaptive Tiled Gustavson Output Reuse for Edge Sparse DNN Accelerators.Adrin Navarro, Jos Cano, Jos L. Abelln, Manuel E. Acacio
2024MICROChaining Transactions for Effective Concurrency Management in Hardware Transactional Memory.Vctor Nicols-Conesa, J. Rubn Titos Gil, Ricardo Fernndez-Pascual, Manuel E. Acacio, Alberto Ros
2023ASPLOSFlexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing.Francisco Muoz-Martnez, Raveesh Garg, Michael Pellauer, Jos L. Abelln, Manuel E. Acacio, Tushar Krishna
2022PDPAnalysis of the Interactions Between ILP and TLP With Hardware Transactional Memory.Vctor Nicols-Conesa, J. Rubn Titos Gil, Ricardo Fernndez-Pascual, Alberto Ros, Manuel E. Acacio
2021MICROITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading.Josu Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
2019EuroParCNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators.Francisco Muoz-Martnez, Jos L. Abelln, Manuel E. Acacio
2018PDPSAWS: Simple and Adaptive Warp Scheduling for Improved Performance in Throughput Processors.Francisco Muoz-Martnez, Manuel E. Acacio
2017ICSWay-combining directory: an adaptive and scalable low-cost coherence directory.J. Rubn Titos Gil, Antonio Flores, Ricardo Fernndez-Pascual, Alberto Ros, Manuel E. Acacio
2014EuroParCharacterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs.Ricardo Fernndez-Pascual, Alberto Ros, Manuel E. Acacio
2013EuroParTowards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support.Mario Lodde, Jos Flich, Manuel E. Acacio
2013ICCSEfficient Dir0B Cache Coherency for Many-Core CMPs.Jos L. Abelln, Alberto Ros, Juan Fernndez, Manuel E. Acacio
2012DATEDesign of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs.Jos L. Abelln, Juan Fernndez Peinador, Manuel E. Acacio, Davide Bertozzi, Daniele Bortolotti, Andrea Marongiu, Luca Benini
2012EuroParDynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols.Mario Lodde, Jos Flich, Manuel E. Acacio
2012HPCAπ-TM: Pessimistic invalidation for scalable lazy hardware transactional memory.Anurag Negi, J. Rubn Titos Gil, Manuel E. Acacio, Jos M. Garca, Per Stenstrm
2012ISLPEDASCIB: adaptive selection of cache indexing bits for removing conflict misses.Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, Jos M. Garca
2012PDPDynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems.Epifanio Gaona-Ramrez, J. Rubn Titos Gil, Manuel E. Acacio, Juan Fernndez
2012SBAC-PADUsing Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs.Alberto Ros, Ricardo Fernndez-Pascual, Manuel E. Acacio
2011ICPPEager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory.Anurag Negi, J. Rubn Titos Gil, Manuel E. Acacio, Jos M. Garca, Per Stenstrm
2011ICSZEBRA: a data-centric, hybrid-policy hardware transactional memory design.J. Rubn Titos Gil, Anurag Negi, Manuel E. Acacio, Jos M. Garca, Per Stenstrm
2010EuroParEvaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs.Alberto Ros, Manuel E. Acacio
2010HiPCEMCAlberto Ros, Blas Cuesta, Ricardo Fernndez-Pascual, Mara Engracia Gmez, Manuel E. Acacio, Antonio Robles, Jos M. Garca, Jos Duato
2010ICPPA G-Line-Based Network for Fast and Efficient Barrier Synchronization in Many-Core CMPs.Jos L. Abelln, Juan Fernndez, Manuel E. Acacio
2010PDPEnergy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects.Antonio Flores, Juan L. Aragn, Manuel E. Acacio
2010SBAC-PADCharacterizing Energy Consumption in Hardware Transactional Memory Systems.Epifanio Gaona-Ramrez, J. Rubn Titos Gil, Juan Fernndez, Manuel E. Acacio
2009EuroParFast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades.Epifanio Gaona-Ramrez, Juan Fernndez, Manuel E. Acacio
2009HiPCDistance-aware round-robin mapping for large NUCA caches.Alberto Ros, Marcelo Cintra, Manuel E. Acacio, Jos M. Garca
2009PDPA Parallel Implementation of the 2D Wavelet Transform Using CUDA.Joaqun Franco, Gregorio Bernab, Juan Fernndez, Manuel E. Acacio
2008DSNA fault-tolerant directory-based cache coherence protocol for CMP architectures.Ricardo Fernndez-Pascual, Jos M. Garca, Manuel E. Acacio, Jos Duato
2008HiPCFault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs.Ricardo Fernndez-Pascual, Jos M. Garca, Manuel E. Acacio, Jos Duato
2008HiPCDirectory-Based Conflict Detection in Hardware Transactional Memory.J. Rubn Titos Gil, Manuel E. Acacio, Jos M. Garca
2008ICCSCharacterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades.Jos L. Abelln, Juan Fernndez, Manuel E. Acacio
2008ICPPAddress Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs.Antonio Flores, Manuel E. Acacio, Juan L. Aragn
2008PDPCellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE.Jos L. Abelln, Juan Fernndez, Manuel E. Acacio
2008PDPCharacterization of Conflicts in Log-Based Transactional Memory (LogTM).J. Rubn Titos Gil, Manuel E. Acacio, Jos Manuel Garca Carrasco
2007AINASim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures.Antonio Flores, Juan L. Aragn, Manuel E. Acacio
2007HiPCEfficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network.Antonio Flores, Juan L. Aragn, Manuel E. Acacio
2007HiPCDirect Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors.Alberto Ros, Manuel E. Acacio, Jos M. Garca
2007HPCAA Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures.Ricardo Fernndez-Pascual, Jos M. Garca, Manuel E. Acacio, Jos Duato
2005EuroParA Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors.Alberto Ros, Manuel E. Acacio, Jos M. Garca
2005HPCCMemory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture.Francisco J. Villa, Manuel E. Acacio, Jos M. Garca
2005PDPOptimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures.Ricardo Fernndez-Pascual, Jos M. Garca, Gregorio Bernab, Manuel E. Acacio
2004ICCSOn the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs.Francisco J. Villa, Manuel E. Acacio, Jos M. Garca
2002PDPReducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration.Manuel E. Acacio, Jos Gonzlez, Jos M. Garca, Jos Duato
2002SCOwner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture.Manuel E. Acacio, Jos Gonzlez, Jos M. Garca, Jos Duato
2001HPCAA New Scalable Directory Architecture for Large-Scale Multiprocessors.Manuel E. Acacio, Jos Gonzlez, Jos M. Garca, Jos Duato
1999PDPTAA Performance Evaluation of P-EDR in Different Parallel Environments.Manuel E. Acacio, Jos M. Garca, Pedro E. Lpez-de-Teruel
1999PDPTAThe MPI-Delphi Interface: A Visual Programming Environment for Clusters of Workstations.Manuel E. Acacio, Pedro E. Lpez-de-Teruel, Jos M. Garca, scar Cnovas Reverte
1999PDPTAThe Parallel EM Algorithm and its Applications in Computer Vision.Pedro E. Lpez-de-Teruel, Jos M. Garca, Manuel E. Acacio