| 2017 | ISCAS | Exploring logic architectures suitable for TFETs devices. | Juan Nez, Maria J. Avedillo |
| 2013 | DSD | Novel Dynamic Gate Topology for Superpipelines in DSM Technologies. | Juan Nez, Maria J. Avedillo, Jos M. Quintana |
| 2010 | DSD | Evaluation of RTD-CMOS Logic Gates. | Juan Nez, Maria J. Avedillo, Jos M. Quintana |
| 2010 | ISCAS | Single phase MOS-NDR mobile networks. | Juan Nez, Maria J. Avedillo, Jos M. Quintana |
| 2009 | ISCAS | Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR. | Juan Nez, Jos M. Quintana, Maria J. Avedillo |
| 2008 | ISCAS | Limits to a correct operation in RTD-based ternary inverters. | Juan Nez, Jos M. Quintana, Maria J. Avedillo |
| 2008 | ISCAS | A novel contribution to the RTD-based threshold logic family. | Hctor Pettenghi, Maria J. Avedillo, Jos M. Quintana |
| 2007 | ISCAS | Non Return Mobile Logic Family. | Hctor Pettenghi, Maria J. Avedillo, Jos M. Quintana |
| 2006 | DSD | Design Guides for a Correct DC Operation in RTD-based Threshold Gates. | Jos M. Quintana, Maria J. Avedillo, Juan Nez |
| 2006 | ISCAS | Self-latching operation limits for MOBILE circuits. | Jos M. Quintana, Maria J. Avedillo, Hctor Pettenghi |
| 2005 | ISCAS | Robust frequency divider based on resonant tunneling devices. | Maria J. Avedillo, Jos M. Quintana, Jos L. Huertas |
| 2004 | DSD | A Threshold Logic Synthesis Tool for RTD Circuits. | Maria J. Avedillo, Jos M. Quintana |
| 2004 | IJCNN | RTD-based compact programmable gates. | Jos M. Quintana, Maria J. Avedillo, Hctor Pettenghi |
| 2004 | ISCAS | Programmable logic gate based on resonant tunnelling devices. | Jos M. Quintana, Maria J. Avedillo, Hctor Pettenghi |
| 2003 | ICANN | Review of Capacitive Threshold Gate Implementations. | Valeriu Beiu, Maria J. Avedillo, Jos M. Quintana |
| 2002 | DATE | An Encoding Technique for Low Power CMOS Implementations of Controllers. | Manuel Martnez, Maria J. Avedillo, Jos M. Quintana, H. S, Manfred Koegst |
| 2002 | ISCAS | Simple parallel weighted order statistic filter implementations. | Maria J. Avedillo, Jos M. Quintana, Esther Rodrguez-Villegas |
| 2002 | ISCAS | Simplified Reed-Muller expressions for residue threshold functions. | Jos M. Quintana, Maria J. Avedillo, Jos L. Huertas |
| 2002 | ISCAS | High-speed low-power logic gates using floating gates. | Esther Rodrguez-Villegas, Jos M. Quintana, Maria J. Avedillo, Adoracin Rueda |
| 2001 | DSD | Two-Criterial Constraint-Driven FSM State Encoding for Low Power. | Manfred Koegst, Steffen Rlke, Gnter Franke, Maria J. Avedillo |
| 2001 | ISCAS | Reed-Muller descriptions of symmetric functions. | Jos M. Quintana, Maria J. Avedillo |
| 1999 | DATE | An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. | Manuel Martnez, Maria J. Avedillo, Jos M. Quintana, Jos L. Huertas |
| 1999 | ISCAS | vMOS-based sorters for multiplier implementations. | Esther Rodrguez-Villegas, Maria J. Avedillo, Jos M. Quintana, Gloria Huertas, Adoracin Rueda |
| 1998 | DATE | A Dynamic Model for the State Assignment Problem. | Manuel Martnez, Maria J. Avedillo, Jos M. Quintana, Jos L. Huertas |
| 1995 | ASPDAC | Optimum PLA folding through boolean satisfiability. | Jos M. Quintana, Maria J. Avedillo, Maria P. Parra, Jos L. Huertas |
| 1993 | ISCAS | Easily Testable PLA-based FSMS. | Maria J. Avedillo, Jos M. Quintana, Jos L. Huertas |