Mario Garca-Valderas
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
20
Venues
4
Active years
2004–2017
Best venue rank
C
Where they publish
Papers
20 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | IOLTS | On-line testing of sensor networks: A case study. | Jos Angel Miranda, Anna Vaskova, Marta Portela-Garca, Mario Garca-Valderas, Celia Lpez-Ongil |
| 2014 | IOLTS | Error masking with approximate logic circuits using dynamic probability estimations. | Antonio Sanchez-Clemente, Luis Entrena, Mario Garca-Valderas |
| 2014 | IOLTS | Permanent faults on LIN networks: On-line test generation. | Anna Vaskova, Marta Portela-Garca, Mario Garca-Valderas, Celia Lpez-Ongil, Matteo Sonza Reorda |
| 2012 | IOLTS | SEU sensitivity of robust communication protocols. | Celia Lpez-Ongil, Marta Portela-Garca, Mario Garca-Valderas, Anna Vaskova, Luis Entrena, Joaqun Rivas-Abalo, Alberto Martn-Ortega, Javier Martinez-Oter, S. Rodriguez-Bustabad, Ignacio Arruego |
| 2012 | IOLTS | Logic masking for SET Mitigation Using Approximate Logic Circuits. | Antonio Sanchez-Clemente, Luis Entrena, Mario Garca-Valderas, Celia Lpez-Ongil |
| 2011 | IOLTS | Evaluation techniques for on-line testing of robust systems based on critical tasks distribution. | Anna Vaskova, Celia Lpez-Ongil, Mario Garca-Valderas, Marta Portela-Garca, Luis Entrena |
| 2010 | IOLTS | An on-line fault detection technique based on embedded debug features. | Michelangelo Grosso, Matteo Sonza Reorda, Marta Portela-Garca, Mario Garca-Valderas, Celia Lpez-Ongil, Luis Entrena |
| 2009 | IOLTS | In-depth analysis of digital circuits against soft errors for selective hardening. | Mario Garca-Valderas, Marta Portela-Garca, Celia Lpez-Ongil, Luis Entrena |
| 2009 | IOLTS | Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. | Alejandro Jimnez-Horas, Enrique San Milln, Celia Lpez-Ongil, Marta Portela-Garca, Mario Garca-Valderas, Luis Entrena |
| 2009 | IOLTS | Briefing power/reliability optimization in embedded software design. | Fabian Vargas, Claudia A. Rocha, Bernardo Pianta, Marta Portela-Garca, Celia Lpez-Ongil, Mario Garca-Valderas, Luis Entrena |
| 2008 | IOLTS | Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. | Celia Lpez-Ongil, Alejandro Jimnez-Horas, Marta Portela-Garca, Mario Garca-Valderas, Enrique San Milln, Luis Entrena |
| 2007 | IOLTS | A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. | Marta Portela-Garca, Celia Lpez-Ongil, Mario Garca-Valderas, Luis Entrena |
| 2006 | DDECS | An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories. | Mario Garca-Valderas, Marta Portela-Garca, Celia Lpez-Ongil, Luis Entrena-Arrontes |
| 2006 | IOLTS | Emulation-based Fault Injection in Circuits with Embedded Memories. | Mario Garca-Valderas, Marta Portela-Garca, Celia Lpez-Ongil, Luis Entrena |
| 2005 | DATE | Techniques for Fast Transient Fault Grading Based on Autonomous Emulation. | Celia Lpez-Ongil, Mario Garca-Valderas, Marta Portela-Garca, Luis Entrena-Arrontes |
| 2005 | FPL | An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation. | Celia Lpez-Ongil, Mario Garca-Valderas, Marta Portela-Garca, Luis Entrena-Arrontes |
| 2005 | IOLTS | Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. | Celia Lpez-Ongil, Mario Garca-Valderas, Marta Portela-Garca, Luis Entrena-Arrontes |
| 2004 | FPL | Power Consumption Reduction Through Dynamic Reconfiguration. | Michael G. Lorenz, Luis Mengibar, Mario Garca-Valderas, Luis Entrena |
| 2004 | FPL | Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. | Mario Garca-Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo |
| 2004 | IOLTS | Transient Fault Emulation of Hardened Circuits in FPGA Platforms. | Mario Garca-Valderas, Celia Lpez-Ongil, Marta Portela-Garca, Luis Entrena |