| 2025 | ACSSC | Implementation and Analysis of Thermometer Encoding in DWN FPGA Accelerators. | Michael Mecik, Martin Kumm |
| 2024 | ARITH | Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs. | Andreas Bttcher, Martin Kumm |
| 2023 | ACSSC | Hardware-Optimal Digital FIR Filters: One ILP to Rule Them all and in Faithfulness Bind Them. | Anastasia Volkova, Rmi Garcia, Florent de Dinechin, Martin Kumm |
| 2023 | ISCAS | More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers. | Martin Hardieck, Tobias Habermann, Fabian Wagner, Michael Mecik, Martin Kumm, Peter Zipf |
| 2022 | FPL | Resource Optimal Squarers for FPGAs. | Andreas Bttcher, Martin Kumm, Florent de Dinechin |
| 2022 | ISCAS | Truncated Multiple Constant Multiplication with Minimal Number of Full Adders. | Rmi Garcia, Anastasia Volkova, Martin Kumm |
| 2021 | ARITH | Resource Optimal Truncated Multipliers for FPGAs. | Andreas Bttcher, Martin Kumm, Florent de Dinechin |
| 2021 | ARITH | Towards Arithmetic-Centered Filter Design. | Florent de Dinechin, Silviu-Ioan Filip, Martin Kumm, Anastasia Volkova |
| 2020 | ARITH | Heuristics for the Design of Large Multipliers for FPGAs. | Andreas Bttcher, Keanu Kullmann, Martin Kumm |
| 2020 | ASPDAC | Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design. | Patrick Sittel, John Wickerson, Martin Kumm, Peter Zipf |
| 2020 | FCCM | Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs. | Lukas Sommer, Lukas Weber, Martin Kumm, Andreas Koch |
| 2019 | ARITH | Table-Based versus Shift-And-Add Constant Multipliers for FPGAs. | Florent de Dinechin, Silviu-Ioan Filip, Martin Kumm, Luc Forget |
| 2019 | EuroPar | Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. | Julian Oppermann, Patrick Sittel, Martin Kumm, Melanie Reuter-Oppermann, Andreas Koch, Oliver Sinnen |
| 2019 | FPGA | Reconfigurable Convolutional Kernels for Neural Networks on FPGAs. | Martin Hardieck, Martin Kumm, Konrad Mller, Peter Zipf |
| 2018 | ARITH | Karatsuba with Rectangular Multipliers for FPGAs. | Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, Peter Zipf |
| 2018 | FPL | ILP-Based Modulo Scheduling and Binding for Register Minimization. | Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Mller, Peter Zipf, Andreas Koch |
| 2017 | ARITH | Resource Optimal Design of Large Multipliers for FPGAs. | Martin Kumm, Johannes Kappauf, Matei Istoan, Peter Zipf |
| 2016 | FPL | Efficient sum of absolute difference computation on FPGAs. | Martin Kumm, Marco Kleinlein, Peter Zipf |
| 2015 | ARITH | An Efficient Softcore Multiplier Architecture for Xilinx FPGAs. | Martin Kumm, Shahid Abbas, Peter Zipf |
| 2014 | FPL | Pipelined compressor tree optimization using integer linear programming. | Martin Kumm, Peter Zipf |
| 2014 | FPL | Pipelined reconfigurable multiplication with constants on FPGAs. | Konrad Mller, Martin Kumm, Marco Kleinlein, Peter Zipf |
| 2013 | FPL | Multiple constant multiplication with ternary adders. | Martin Kumm, Martin Hardieck, Jens Willkomm, Peter Zipf, Uwe Meyer-Baese |
| 2013 | ISCAS | Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs. | Martin Kumm, Konrad Mller, Peter Zipf |
| 2013 | ISCAS | Reconfigurable FIR filter using distributed arithmetic on FPGAs. | Martin Kumm, Konrad Mller, Peter Zipf |
| 2012 | FPL | Reduced complexity single and multiple constant multiplication in floating point precision. | Martin Kumm, Katharina Liebisch, Peter Zipf |
| 2012 | FPL | Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system. | Michael Kunz, Martin Kumm, Martin Heide, Peter Zipf |
| 2012 | ISCAS | Pipelined adder graph optimization for high speed multiple constant multiplication. | Martin Kumm, Peter Zipf, Mathias Faust, Chip-Hong Chang |
| 2008 | FPL | Digital hilbert transformers for FPGA-based phase-locked loops. | Martin Kumm, M. Shahab Sanjari |