Masakatsu Suda
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
1
Active years
2002–2009
Best venue rank
A
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2009 | ITC | Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing. | Tasuku Fujibe, Masakatsu Suda, Kazuhiro Yamamoto, Yoshihito Nagata, Kazuhiro Fujita, Daisuke Watanabe, Toshiyuki Okayasu |
| 2006 | ITC | Multi Strobe Circuit for 2.133GHz Memory Test System. | Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu, Hirokatsu Niijima, Koichi Tanaka |
| 2005 | ITC | CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system. | Masakatsu Suda, Kazuhiro Yamamoto, Toshiyuki Okayasu, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe |
| 2004 | ITC | 34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System. | Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu |
| 2002 | ITC | CMOS Circuit Technology for Precise GHz Timing Generator. | Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto |