Masanori Hariyama
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
11
Venues
6
Active years
1998–2025
Best venue rank
A*
Where they publish
Papers
11 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ASPDAC | Large-Scale AGV Routing Based on Multi-FPGA SQA Acceleration. | Thinh NguyenQuang, Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masayuki Ohzeki |
| 2022 | PDCAT | Word2Vec FPGA Accelerator Based on Spatial and Temporal Parallelism. | Hasitha Muthumala Waidyasooriya, Shutaro Ishihara, Masanori Hariyama |
| 2020 | SAC | Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories. | Chia-Yin Liu, Yi-Jung Chen, Masanori Hariyama |
| 2019 | ISCAS | FPGA-Based Acceleration of Word2vec using OpenCL. | Taisuke Ono, Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa |
| 2017 | SNPD | Architecture of an FPGA accelerator for LDA-based inference. | Taisuke Ono, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tsukasa Ishigaki |
| 2012 | ISCAS | FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators. | Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama |
| 2012 | ISCAS | Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. | Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
| 2011 | ASPDAC | An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. | Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
| 2009 | ASPDAC | A low-power FPGA based on autonomous fine-grain power-gating. | Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
| 2001 | ICRA | VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. | Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama |
| 1998 | ICRA | Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. | Masanori Hariyama, Michitaka Kameyama |