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Mateusz Majer

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

8

Venues

3

Active years

2004–2008

Best venue rank

B

Where they publish

Papers

8 indexed papers, newest first.

YearVenueTitleAuthors
2008FPLFine grain reconfigurable architectures.Josef Angermeier, Mateusz Majer, Jrgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hbner, Jrgen Becker, Enno Lbbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker
2008RSPCo-design Architecture and Implementation for Point-Based Rendering on FPGAs.Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jrgen Teich
2006FPLMinimizing Communication Cost for Reconfigurable Slot Modules.Sndor P. Fekete, Jan van der Veen, Mateusz Majer, Jrgen Teich
2006FPLAn FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization.Mateusz Majer
2005FCCMThe Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform.Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, Andr Linarth, Jrgen Teich, Sndor P. Fekete, Jan van der Veen
2005FPLDyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices.Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jrgen Teich, Sndor P. Fekete, Jan van der Veen
2005RSPA Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices.Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jrgen Teich, Sndor P. Fekete, Jan van der Veen
2004FPLA Dynamic NoC Approach for Communication in Reconfigurable Devices.Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jrgen Teich