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Matheus T. Moreira

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

8

Venues

4

Active years

2013–2025

Best venue rank

A*

Where they publish

Papers

8 indexed papers, newest first.

YearVenueTitleAuthors
2025DACLLMs: A Driving Force in Next Generation Digital Design Automation.Matheus T. Moreira, Aram H. Markosyan, Chris Cummins, Warren Hunt, Gabriel Synnaeve, Edith Beign
2021DACSLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping.Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amar, Cunxi Yu, Pierre-Emmanuel Gaillardon
2021ISCASQuasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison.Taciano A. Rodolfo, Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans
2020ISCASLeveraging QDI Robustness to Simplify the Design of IoT Circuits.Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Sergio Bampi, Ney Laert Vilar Calazans
2018ISCASAn LSSD Compliant Scan Cell for Flip-Flops.Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Fernando Gehm Moraes, Alexandre M. Amory
2017ISCASPost-processing of supergate networks aiming cell layout optimization.Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.
2015VLSIDAnalysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits.Guilherme Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, Peter A. Beerel, Ney Laert Vilar Calazans
2013RSPBaBaNoC: An asynchronous network-on-chip described in Balsa.Matheus T. Moreira, Felipe G. Magalhaes, Matheus Gibiluka, Fabiano Hessel, Ney Laert Vilar Calazans