Mathias Soeken
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
98
Venues
19
Active years
2010–2025
Best venue rank
A*
Where they publish
Papers
98 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ASPDAC | Back-end-aware Fault-tolerant Quantum Oracle Synthesis. | Mingfei Yu, Alessandro Tempia Calvino, Mathias Soeken, Giovanni De Micheli |
| 2025 | QCE | Improving Hardware Requirements for Fault-Tolerant Quantum Computing by Optimizing Error Budget Distributions. | Tobias V. Forster, Nils Quetschlich, Mathias Soeken, Robert Wille |
| 2025 | QCE | A New Perspective of Constructing Resource-Efficient Data-Lookup Quantum Oracles. | Mingfei Yu, Mathias Soeken, Giovanni De Micheli |
| 2024 | QCE | Utilizing Resource Estimation for the Development of Quantum Computing Applications. | Nils Quetschlich, Mathias Soeken, Prakash Murali, Robert Wille |
| 2023 | SC | Using Azure Quantum Resource Estimator for Assessing Performance of Fault Tolerant Quantum Computation. | Wim van Dam, Mariia Mykhailova, Mathias Soeken |
| 2022 | DAC | Automatic oracle generation in microsoft's quantum development kit using QIR and LLVM passes. | Mathias Soeken, Mariia Mykhailova |
| 2021 | DATE | A Resource Estimation and Verification Workflow in Q# Special session paper. | Mathias Soeken, Mariia Mykhailova, Vadym Kliuchnikov, Christopher E. Granade, Alexander Vaschillo |
| 2021 | QCE | Testing Quantum Programs using Q# and Microsoft Quantum Development Kit. | Mariia Mykhailova, Mathias Soeken |
| 2020 | DATE | Exact DAG-Aware Rewriting. | Heinz Riener, Alan Mishchenko, Mathias Soeken |
| 2020 | DATE | Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper). | Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli |
| 2020 | DATE | A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. | Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amar, Giovanni De Micheli |
| 2020 | ISCAS | Enumerating Optimal Quantum Circuits using Spectral Classification. | Giulia Meuli, Mathias Soeken, Martin Roetteler, Giovanni De Micheli |
| 2020 | PQCrypto | Improved Quantum Circuits for Elliptic Curve Discrete Logarithms. | Thomas Hner, Samuel Jaques, Michael Naehrig, Martin Roetteler, Mathias Soeken |
| 2020 | QCE | Quantum Circuits for Functionally Controlled NOT Gates. | Mathias Soeken, Martin Roetteler |
| 2019 | ASPDAC | Structural rewriting in XOR-majority graphs. | Zhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli |
| 2019 | DAC | Scalable Generic Logic Synthesis: One Approach to Rule Them All. | Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amar, Giovanni De Micheli, Mathias Soeken |
| 2019 | DAC | Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications. | Eleonora Testa, Mathias Soeken, Luca G. Amar, Giovanni De Micheli |
| 2019 | DATE | Reversible Pebbling Game for Quantum Memory Management. | Giulia Meuli, Mathias Soeken, Martin Roetteler, Nikolaj S. Bjrner, Giovanni De Micheli |
| 2019 | DATE | On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis. | Heinz Riener, Winston Haaswijk, Alan Mishchenko, Giovanni De Micheli, Mathias Soeken |
| 2019 | DATE | Compiling Permutations for Superconducting QPUs. | Mathias Soeken, Fereshte Mozafari, Bruno Schmitt, Giovanni De Micheli |
| 2019 | DATE | Scalable Boolean Methods in a Modern Synthesis Flow. | Eleonora Testa, Luca G. Amar, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2019 | ICCAD | The Role of Multiplicative Complexity in Compiling Low $T$-count Oracle Circuits. | Giulia Meuli, Mathias Soeken, Earl T. Campbell, Martin Roetteler, Giovanni De Micheli |
| 2019 | ISCAS | Exact Synthesis of Boolean Functions in Majority-of-Five Forms. | Zhufei Chu, Winston Haaswijk, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli |
| 2018 | ASPDAC | Functional decomposition using majority. | Zhufei Chu, Mathias Soeken, Yinshui Xia, Giovanni De Micheli |
| 2018 | ASPDAC | A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis. | Giulia Meuli, Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli |
| 2018 | DAC | SAT based exact synthesis using DAG topology families. | Winston Haaswijk, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli |
| 2018 | DAC | Canonical computation without canonical representation. | Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amar, Antun Domic |
| 2018 | DATE | Improvements to boolean resynthesis. | Luca Gaetano Amar, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli |
| 2018 | DATE | Programming quantum computers using design automation. | Mathias Soeken, Thomas Hner, Martin Roetteler |
| 2018 | DATE | Practical exact synthesis. | Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amar, Robert K. Brayton, Giovanni De Micheli |
| 2018 | ICCAD | Majority logic synthesis. | Luca G. Amar, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken |
| 2018 | ISCAS | Deep Learning for Logic Optimization Algorithms. | Winston Haaswijk, Edo Collins, Benoit Seguin, Mathias Soeken, Frdric Kaplan, Sabine Ssstrunk, Giovanni De Micheli |
| 2018 | RC | Quantum Circuits for Floating-Point Arithmetic. | Thomas Hner, Mathias Soeken, Martin Roetteler, Krysta M. Svore |
| 2018 | RC | SAT-based {CNOT, T} Quantum Circuit Synthesis. | Giulia Meuli, Mathias Soeken, Giovanni De Micheli |
| 2017 | ASPDAC | Multi-level logic benchmarks: An exactness study. | Luca Gaetano Amar, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2017 | ASPDAC | A novel basis for logic rewriting. | Winston Haaswijk, Mathias Soeken, Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2017 | DAC | Hierarchical Reversible Logic Synthesis Using LUTs. | Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli |
| 2017 | DATE | Endurance management for resistive Logic-In-Memory computing architectures. | Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler |
| 2017 | DATE | Busy man's synthesis: Combinational delay optimization with SAT. | Mathias Soeken, Giovanni De Micheli, Alan Mishchenko |
| 2017 | DATE | Design automation and design space exploration for quantum computers. | Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli |
| 2017 | DATE | Wave pipelining for majority-based beyond-CMOS technologies. | Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amar, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins |
| 2017 | GECCO | An adaptive prioritized | Saeideh Shirinzadeh, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2017 | ICCAD | Enabling exact delay synthesis. | Luca Gaetano Amar, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli |
| 2017 | ISCAS | RM3 based logic synthesis (Special session paper). | Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2016 | ASPDAC | BDD minimization for approximate computing. | Mathias Soeken, Daniel Groe, Arun Chandrasekharan, Rolf Drechsler |
| 2016 | DAC | Precise error determination of approximated components in sequential circuits with model checking. | Arun Chandrasekharan, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2016 | DAC | Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis. | Mathias Soeken, Anupam Chattopadhyay |
| 2016 | DAC | An MIG-based compiler for programmable logic-in-memory architectures. | Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amar, Rolf Drechsler, Giovanni De Micheli |
| 2016 | DATE | Formal verification of integer multipliers by combining Grbner basis with logic reduction. | Amr A. R. Sayed-Ahmed, Daniel Groe, Ulrich Khne, Mathias Soeken, Rolf Drechsler |
| 2016 | DATE | Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. | Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler |
| 2016 | DATE | Optimizing Majority-Inverter Graphs with functional hashing. | Mathias Soeken, Luca Gaetano Amar, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2016 | DDECS | Multi-objective BDD optimization for RRAM based circuit design. | Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler |
| 2016 | FMCAD | Equivalence checking using Grbner bases. | Amr A. R. Sayed-Ahmed, Daniel Groe, Mathias Soeken, Rolf Drechsler |
| 2016 | FPL | Fast hierarchical NPN classification. | Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko |
| 2016 | GECCO | Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. | Saeideh Shirinzadeh, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2016 | ICCAD | Approximation-aware rewriting of AIGs for error tolerant applications. | Arun Chandrasekharan, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2016 | ICCAD | Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. | Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne |
| 2016 | ICCAD | Multilevel design understanding: from specification to logic (invited paper). | Sandip Ray, Ian G. Harris, Grschwin Fey, Mathias Soeken |
| 2016 | ISCAS | An extension of transformation-based reversible and quantum circuit synthesis. | Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller |
| 2016 | RC | Enumeration of Reversible Functions and Its Application to Circuit Complexity. | Mathias Soeken, Nabila Abdessaied, Giovanni De Micheli |
| 2016 | RC | A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis. | Mathias Soeken, Gerhard W. Dueck, D. Michael Miller |
| 2016 | SAT | Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. | Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli |
| 2015 | DDECS | Requirement Phrasing Assistance Using Automatic Quality Assessment. | Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler |
| 2015 | FMCAD | Simulation Graphs for Reverse Engineering. | Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton |
| 2015 | GECCO | Multi-Objective BDD Optimization with Evolutionary Algorithms. | Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler |
| 2015 | MODELS | Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses. | Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler |
| 2015 | RC | Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition. | Nabila Abdessaied, Mathias Soeken, Rolf Drechsler |
| 2015 | RC | Ricercar: A Language for Describing and Rewriting Reversible Circuits with Ancillae and Its Permutation Semantics. | Michael Kirkedal Thomsen, Robin Kaarsgaard, Mathias Soeken |
| 2015 | TAP | Coverage of OCL Operation Specifications and Invariants. | Mathias Soeken, Julia Seiter, Rolf Drechsler |
| 2014 | FDL | MetaSMT: a unified interface to SMT-LIB2. | Heinz Riener, Mathias Soeken, Clemens Werther, Grschwin Fey, Rolf Drechsler |
| 2014 | FDL | Automating the translation of assertions using natural language processing techniques. | Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris, Rolf Drechsler |
| 2014 | ICCAD | Automated and quality-driven requirements engineering. | Rolf Drechsler, Mathias Soeken, Robert Wille |
| 2014 | RC | Quantum Circuit Optimization by Hadamard Gate Reduction. | Nabila Abdessaied, Mathias Soeken, Rolf Drechsler |
| 2014 | RC | Mapping NCV Circuits to Optimized Clifford+T Circuits. | D. Michael Miller, Mathias Soeken, Rolf Drechsler |
| 2014 | TAP | Behaviour Driven Development for Tests and Verification. | Melanie Diepenbeck, Ulrich Khne, Mathias Soeken, Rolf Drechsler |
| 2013 | ASPDAC | Improving the mapping of reversible circuits to quantum circuits using multiple target lines. | Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler |
| 2013 | DATE | Determining relevant model elements for the verification of UML/OCL specifications. | Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler |
| 2013 | DATE | Towards a generic verification methodology for system models. | Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler |
| 2013 | DDECS | Hardware-Software Co-Visualization: Developing systems in the holodeck. | Rolf Drechsler, Mathias Soeken |
| 2013 | GI | Text statt C++: Automatisierung des Systementwurfs mit Hilfe natrlicher Sprachverarbeitung. | Rolf Drechsler, Mathias Soeken, Robert Wille |
| 2013 | ICSE | Towards automatic scenario generation from coverage information. | Melanie Diepenbeck, Mathias Soeken, Daniel Groe, Rolf Drechsler |
| 2013 | RC | Reducing the Depth of Quantum Circuits Using Additional Circuit Lines. | Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler |
| 2013 | RC | White Dots do Matter: Rewriting Reversible Logic Circuits. | Mathias Soeken, Michael Kirkedal Thomsen |
| 2012 | ASPDAC | Synthesis of reversible circuits with minimal lines for large functions. | Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler |
| 2012 | DATE | Eliminating invariants in UML/OCL models. | Mathias Soeken, Robert Wille, Rolf Drechsler |
| 2012 | DATE | Debugging of inconsistent UML/OCL models. | Robert Wille, Mathias Soeken, Rolf Drechsler |
| 2012 | FDL | Formal Specification Level: Towards verification-driven design based on natural language processing. | Rolf Drechsler, Mathias Soeken, Robert Wille |
| 2012 | FDL | Formal Specification Level. | Rolf Drechsler, Mathias Soeken, Robert Wille |
| 2012 | RC | Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams. | Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler |
| 2012 | RC | Using | Mathias Soeken, Robert Wille, Shin-ichi Minato, Rolf Drechsler |
| 2011 | DATE | Verifying dynamic aspects of UML models. | Mathias Soeken, Robert Wille, Rolf Drechsler |
| 2011 | DDECS | Automatic property generation for the formal verification of bus bridges. | Mathias Soeken, Ulrich Khne, Martin Freibothe, Grschwin Fey, Rolf Drechsler |
| 2011 | MODELS | Towards automatic determination of problem bounds for object instantiation in static model verification. | Mathias Soeken, Robert Wille, Rolf Drechsler |
| 2011 | RC | RevKit: An Open Source Toolkit for the Design of Reversible Circuits. | Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler |
| 2011 | TAP | Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models. | Mathias Soeken, Robert Wille, Rolf Drechsler |
| 2010 | DAC | Reducing the number of lines in reversible circuits. | Robert Wille, Mathias Soeken, Rolf Drechsler |
| 2010 | DATE | Verifying UML/OCL models using Boolean satisfiability. | Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler |
| 2010 | DDECS | Window optimization of reversible and quantum circuits. | Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |