| 2020 | ICPP | HCAPP: Scalable Power Control for Heterogeneous 2.5D Integrated Systems. | Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella |
| 2019 | HPCC | Tuning Network I/O Processing to Achieve Performance and Energy Objectives of Latency Critical Workloads. | Sambit Kumar Shukla, Dipak Ghosal, Matthew K. Farrens |
| 2018 | HiPC | Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP. | Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella |
| 2018 | ISCA | A case for exposing extra-architectural state in the ISA: position paper. | Jason Lowe-Power, Venkatesh Akella, Matthew K. Farrens, Samuel T. King, Christopher J. Nitta |
| 2017 | ICCD | Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing. | Kramer Straube, Christopher Nitta, Raj Amirtharajah, Matthew K. Farrens, Venkatesh Akella |
| 2015 | NSS | Performance Analysis of Real-Time Covert Timing Channel Detection Using a Parallel System. | Ross K. Gegan, Rennie Archibald, Matthew K. Farrens, Dipak Ghosal |
| 2014 | SC | Analysis of the effect of core affinity on high-throughput flows. | Nathan Hanford, Vishal Ahuja, Matthew K. Farrens, Dipak Ghosal, Mehmet Balman, Eric Pouyoul, Brian Tierney |
| 2013 | SC | Characterizing the impact of end-system affinities on the end-to-end performance of high-speed flows. | Nathan Hanford, Vishal Ahuja, Mehmet Balman, Matthew K. Farrens, Dipak Ghosal, Eric Pouyoul, Brian Tierney |
| 2012 | CCGRID | Minimizing the Data Transfer Time Using Multicore End-System Aware Flow Bifurcation. | Vishal Ahuja, Dipak Ghosal, Matthew K. Farrens |
| 2011 | HPCA | Addressing system-level trimming issues in on-chip nanophotonic networks. | Christopher Nitta, Matthew K. Farrens, Venkatesh Akella |
| 2011 | HPDC | Introspective end-system modeling to optimize the transfer time of rate based protocols. | Vishal Ahuja, Amitabha Banerjee, Matthew K. Farrens, Dipak Ghosal, Giuseppe Serazzi |
| 2011 | MICRO | Resilient microring resonator based photonic networks. | Christopher Nitta, Matthew K. Farrens, Venkatesh Akella |
| 2008 | ICCD | Design and evaluation of an optical CPU-DRAM interconnect. | Amit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella |
| 2008 | ICCD | Techniques for increasing effective data bandwidth. | Christopher Nitta, Matthew K. Farrens |
| 2000 | EuroPar | The Decoupled-Style Prefetch Architecture (Research Note). | Kevin D. Rich, Matthew K. Farrens |
| 2000 | EuroPar | Code Partitioning in Decoupled Compilers. | Kevin D. Rich, Matthew K. Farrens |
| 2000 | HPCA | Branch Transition Rate: A New Metric for Improved Branch Classification Analysis. | Michael Haungs, Phil Sallee, Matthew K. Farrens |
| 2000 | ISCA | HLS: combining statistical and symbolic simulation to guide microprocessor designs. | Mark Oskin, Frederic T. Chong, Matthew K. Farrens |
| 2000 | MICRO | Eager writeback - a technique for improving bandwidth utilization. | Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens |
| 1999 | MICRO | Exploiting ILP in Page-based Intelligent Memory. | Mark Oskin, Justin Hensley, Diana Keen, Frederic T. Chong, Matthew K. Farrens, Aneet Chopra |
| 1998 | ICS | Utilizing Reuse Information in Data Cache Management. | Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens |
| 1998 | WCAE | The architecture curriculum at UC-Davis. | Matthew K. Farrens |
| 1995 | MICRO | A modified approach to data cache management. | Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun |
| 1994 | ISCA | A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. | Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun |
| 1993 | MICRO | A comparision of superscalar and decoupled access/execute architectures. | Matthew K. Farrens, Pius Ng, Phil Nico |
| 1993 | MICRO | Techniques for extracting instruction level parallelism on MIMD architectures. | Gary S. Tyson, Matthew K. Farrens |
| 1992 | ISCA | A partitioned translation lookaside buffer approach to reducing address bandwith. | Matthew K. Farrens, Arvin Park, Rob Fanfelle, Pius Ng, Gary S. Tyson |
| 1992 | MICRO | Modifying VM hardware to reduce address pin requirements. | Matthew K. Farrens, Arvin Park, Gary S. Tyson |
| 1992 | MICRO | MISC: a Multiple Instruction Stream Computer. | Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun |
| 1991 | ISCA | Dynamic Base Register Caching: A Technique for Reducing Address Bus Width. | Matthew K. Farrens, Arvin Park |
| 1991 | ISCA | Strategies for Achieving Improved Processor Throughput. | Matthew K. Farrens, Andrew R. Pleszkun |
| 1991 | MICRO | An Analysis of the Information Content of Address Reference Streams. | Jeffrey C. Becker, Arvin Park, Matthew K. Farrens |
| 1991 | MICRO | Workload and Implementation Considerations for Dynamic Base Register Caching. | Matthew K. Farrens, Arvin Park |
| 1991 | SC | Alleviation of tree saturation in multistage interconnection networks. | Matthew K. Farrens, Brad Wetmore, Allison Woodruff |
| 1990 | MICRO | An evaluation of functional unit lengths for single-chip processors. | Matthew K. Farrens, Andrew R. Pleszkun |
| 1990 | MICRO | Address compression through base register caching. | Arvin Park, Matthew K. Farrens |
| 1989 | ISCA | Improving Performance of Small On-Chip Instruction Caches. | Matthew K. Farrens, Andrew R. Pleszkun |