Maurice Jamieson
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
6
Active years
2020–2026
Best venue rank
A*
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | FCCM | Towards Compiler-Driven Dynamic Partial Reconfiguration with MLIR. | Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson, Nicolas Bohm Agostini, Ankur Limaye, Vito Giovanni Castellana, Joseph B. Manzano, Antonino Tumeo |
| 2026 | FPGA | Towards Scheduling of Pipelined Dataflow Graphs in MLIR. | Gabriel Rodriguez-Canal, Nicolas Bohm Agostini, Ankur Limaye, Vito Giovanni Castellana, Joseph B. Manzano, Antonino Tumeo, Maurice Jamieson, Nick Brown |
| 2024 | ASPLOS | A shared compilation stack for distributed-memory parallelism in stencil DSLs. | George Bisbas, Anton Lydike, Emilien Bauer, Nick Brown, Mathieu Fehr, Lawrence Mitchell, Gabriel Rodriguez-Canal, Maurice Jamieson, Paul H. J. Kelly, Michel Steuwer, Tobias Grosser |
| 2023 | SC | Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang. | Nick Brown, Maurice Jamieson, Anton Lydike, Emilien Bauer, Tobias Grosser |
| 2023 | SC | Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU. | Nick Brown, Maurice Jamieson, Joseph K. L. Lee, Paul Wang |
| 2023 | SC | Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA. | Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson, Emilien Bauer, Anton Lydike, Tobias Grosser |
| 2022 | EuroPar | Performance of the Vipera Framework for DSLs on Micro-Core Architectures. | Maurice Jamieson, Nick Brown |
| 2021 | CC | Compact native code generation for dynamic languages on micro-core architectures. | Maurice Jamieson, Nick Brown |
| 2020 | SC | Benchmarking micro-core architectures for detecting disasters at the edge. | Maurice Jamieson, Nick Brown |