Meng-Ting Tsai
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2005–2015
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | DATE | Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects. | Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng |
| 2015 | ITC | Monitoring the delay of long interconnects via distributed TDC. | Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng |
| 2006 | ISCAS | A frequency synthesizer realized by a transformer-based voltage-controlled oscillator for IEEE 802.11a/b/g channels. | Meng-Ting Tsai, Ching-Yuan Yang |
| 2006 | ISCAS | A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique. | Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, Ching-Yuan Yang |
| 2005 | ISCAS | A high-frequency phase-compensation fractional-N frequency synthesizer. | Ching-Yuan Yang, Jen-Wen Chen, Meng-Ting Tsai |