A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique.
Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, Ching-Yuan Yang
Browse the full ISCAS paper archive.
Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, Ching-Yuan Yang
Browse the full ISCAS paper archive.