Menka Tewani
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2008–2008
Best venue rank
National
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2008 | VLSID | 0.35, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. | Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani |