0.35, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops.
Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani
Browse the full VLSID paper archive.
Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani
Browse the full VLSID paper archive.