Vinay Bhaskar Chandratre
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
1
Active years
2008–2011
Best venue rank
National
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | VLSID | Extraction of Aspect Ratio for Non-Manhattan CMOS Devices. | Shiv Kumar, Vinay Bhaskar Chandratre, Sudheer K. Mohammed, C. K. Pithawa |
| 2010 | VLSID | An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops. | Balaji Srinivasan, Vinay Bhaskar Chandratre |
| 2008 | VLSID | 0.35, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. | Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani |