Michal Kekely
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
5
Active years
2017–2023
Best venue rank
A*
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2023 | DDECS | Optimizing Packet Classification on FPGA. | Michal Kekely, Jan Korenek |
| 2020 | DSD | Pipelined ALU for effective external memory access in FPGA. | Toms Benes, Michal Kekely, Karel Hynek, Toms Cejka |
| 2018 | CCS | 200 Gbps Hardware Accelerated Encryption System for FPGA Network Cards. | Zdenek Martinasek, Jan Hajny, David Smekal, Lukas Malina, Denis Matousek, Michal Kekely, Nele Mentens |
| 2018 | DSD | Memory Aware Packet Matching Architecture for High-Speed Networks. | Michal Kekely, Lukas Kekely, Jan Korenek |
| 2018 | FPGA | Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. | Jakub Cabal, Pavel Bencek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek |
| 2017 | DSD | Packet Classification with Limited Memory Resources. | Michal Kekely, Jan Korenek |
| 2017 | FPL | Line rate programmable packet processing in 100Gb networks. | Pavel Bencek, Viktor Pus, Jan Korenek, Michal Kekely |
| 2017 | FPL | Mapping of P4 match action tables to FPGA. | Michal Kekely, Jan Korenek |