| 2022 | ICCS | Approximate Function Classification. | Martin Lukac, Krzysztof Podlaski, Michitaka Kameyama |
| 2020 | ICPR | Selecting Algorithms Without Meta-features. | Martin Lukac, Ayazkhan Bayanov, Albina Li, Kamila Abdiyeva, Nadira Izbassarova, Magzhan Gabidolla, Michitaka Kameyama |
| 2018 | SMC | High-Accuracy Scene Recognition and Its Application to Highly-Safe Intelligent Systems. | Kenichi Takada, Michitaka Kameyama |
| 2017 | SMC | Live-feeling communication: Multi-algorithm approach to the estimation of human intentions. | Martin Lukac, Michitaka Kameyama, Yevgeniya Migranova |
| 2014 | DSD | Minimizing Reversible Circuits in the 2n Scheme Using Two and Three Bits Patterns. | Martin Lukac, Maher Hawash, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf |
| 2012 | ISCAS | FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators. | Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama |
| 2012 | ISCAS | Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. | Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
| 2011 | ASPDAC | An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. | Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
| 2011 | ISDA | Non-blocking tag scanning for passive RFID localization. | Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama |
| 2010 | CEC | Evolutionary quantum logic synthesis of Boolean reversible logic circuits embedded in ternary quantum space using structural restrictions. | Martin Lukac, Marek A. Perkowski, Michitaka Kameyama |
| 2009 | ASPDAC | A low-power FPGA based on autonomous fine-grain power-gating. | Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
| 2005 | ISCAS | VLSI architecture based on packet data transfer scheme and its application. | Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi |
| 2001 | ICRA | VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. | Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama |
| 2000 | PRDC | Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. | Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama |
| 1998 | ICRA | Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. | Masanori Hariyama, Michitaka Kameyama |
| 1997 | ASPDAC | Low-power multiple-valued current-mode integrated circuit with current-source control and its application. | Takahiro Hanyu, Satoshi Kazama, Michitaka Kameyama |
| 1993 | ICRA | 2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control. | Yoshichika Fujioka, Michitaka Kameyama |
| 1991 | ICCD | High-Performance VLSI Processor for Robot Inverse Dynamics Computation. | Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi |
| 1989 | ICRA | Implementation of a high performance LSI for inverse kinematics computation. | Michitaka Kameyama, Takao Matsumoto, Hideki Egami, Tatsuo Higuchi |