Mincent Lee
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
3
Active years
2012–2020
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | ITC | A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. | Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang |
| 2019 | ITC | High Quality Test Methodology for Highly Reliable Devices. | Hao Chen, Mincent Lee, Liang-Yen Chen, Min-Jer Wang |
| 2016 | DAC | Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. | Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang |
| 2014 | ITC | Redundancy architectures for channel-based 3D DRAM yield improvement. | Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang |
| 2012 | ITC | A memory yield improvement scheme combining built-in self-repair and error correction codes. | Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang |
| 2012 | VTS | Cost modeling and analysis for interposer-based three-dimensional IC. | Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu |
| 2012 | VTS | A Memory Failure Pattern Analyzer for memory diagnosis and repair. | Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu |