Ming-Chien Tsai
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2008–2012
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | ISCAS | An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. | Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu |
| 2009 | ASPDAC | A full-synthesizable high-precision built-in delay time measurement circuit. | Ming-Chien Tsai, Ching-Hwa Cheng |
| 2008 | VTS | An All-Digital High-Precision Built-In Delay Time Measurement Circuit. | Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang |