| 2023 | ISCAS | Radiation-hardened triple-modular redundant field programmable gate array with a two-phase clock. | Minoru Watanabe |
| 2021 | ISCAS | Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs. | Kurea Murakami, Minoru Watanabe |
| 2019 | ETFA | FPGA implementation of a robot control algorithm. | Yusuke Takaki, Kohei Nagasu, Shin Abiko, Minoru Watanabe, Kentaro Sano |
| 2018 | ISCAS | High total-ionizing-dose tolerance field programmable gate array. | Takumi Fujimori, Minoru Watanabe |
| 2017 | DASC | Holographic Memory Calculation FPGA Accelerator for Optically Reconfigurable Gate Arrays. | Takumi Fujimori, Minoru Watanabe |
| 2016 | HPCC | A 200 Mrad Radiation Tolerance of a Polymer-Dispersed Liquid Crystal Holographic Memory. | Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara |
| 2016 | VLSID | Reconfiguration Performance Recovery on Optically Reconfigurable Gate Arrays. | Tomoya Akabe, Minoru Watanabe |
| 2014 | ISCAS | Image recognition system using an optical Fourier transform on a dynamically reconfigurable vision architecture. | Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito |
| 2013 | FPL | Image recognition operation on a dynamically reconfigurable vison architecture. | Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito |
| 2013 | ISCAS | 0.18 μm CMOS process photodiode memory. | Takayuki Kubota, Minoru Watanabe |
| 2013 | ISCAS | Dependability-increasing technique for a multi-context optically reconfigurable gate array. | Akira Tanigawa, Minoru Watanabe |
| 2012 | FPL | A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function. | Takashi Yoza, Minoru Watanabe |
| 2011 | FPL | Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory. | Takahiro Watanabe, Minoru Watanabe |
| 2010 | FPL | Dynamically Reconfigurable Vision-Chip Architecture. | Maki Yasuda, Minoru Watanabe |
| 2010 | ISCAS | A 100-context optically reconfigurable gate array. | Mao Nakajima, Minoru Watanabe |
| 2009 | ASPDAC | An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture. | Daisaku Seto, Minoru Watanabe |
| 2009 | FPL | Mems optically reconfigurable gate array. | Hironobu Morita, Minoru Watanabe |
| 2009 | ISCAS | Fast Reconfiguration Experiments of an Optically Differential Reconfigurable Gate Array with Nine Configuration Contexts. | Mao Nakajima, Minoru Watanabe |
| 2008 | VLSID | An Acceleration and Optimization Method for Optical Reconfiguration. | Minoru Watanabe, Naoki Yamaguchi |
| 2008 | VLSID | An Optical Reconfiguration System with Four Contexts. | Naoki Yamaguchi, Minoru Watanabe |
| 2007 | ASPDAC | A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. | Minoru Watanabe, Fuminori Kobayashi |
| 2007 | ISCAS | Holographic memory reconfigurable VLSI. | Minoru Watanabe, Fuminori Kobayashi |
| 2006 | ASPDAC | A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. | Minoru Watanabe, Fuminori Kobayashi |
| 2006 | FPL | A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. | Minoru Watanabe, Fuminori Kobayashi |
| 2005 | ISCAS | A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35m CMOS technology. | Minoru Watanabe, Fuminori Kobayashi |
| 2004 | FPL | A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. | Minoru Watanabe, Fuminori Kobayashi |
| 2004 | VLSID | An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation. | Minoru Watanabe, Fuminori Kobayashi |