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Mitsumasa Koyanagi

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

7

Venues

6

Active years

1998–2011

Best venue rank

A*

Where they publish

Papers

7 indexed papers, newest first.

YearVenueTitleAuthors
2011ISLPED3D super chip technology to achieve low-power and high-performance system-on-a chip.Mitsumasa Koyanagi
2009ASPDACThree-dimensional integration technology and integrated systems.Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka
2006IROSDevelopment of a High Speed Vision System for Mobile Robots.Atsushi Konno, Ryo Uchikura, Toshiyuki Ishihara, Teppei Tsujita, Takeaki Sugimura, Jun Deguchi, Mitsumasa Koyanagi, Masaru Uchiyama
2004AINADesign of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory.Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi
2004PDCATDesign and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip.Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi
2002DACNanometer design: what hurts next...?Robert W. Brodersen, Anthony M. Hill, John Kibarian, Desmond Kirkpatrick, Mark A. Lavin, Mitsumasa Koyanagi
1998ASPDACA New Multiport Memory for High Performance Parallel Processor System with Shared Memory.Keiichi Hirano, Taizou Ono, Hiroyuki Kurino, Mitsumasa Koyanagi