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Morihiro Kuga

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

12

Venues

5

Active years

1989–2022

Best venue rank

A*

Where they publish

Papers

12 indexed papers, newest first.

YearVenueTitleAuthors
2022FPLFPL Demo: An FPGA-IP Prototype Chip for MEC devices.Morihiro Kuga, Masahiro Iida, Hideharu Amano
2014FPLA logic cell architecture exploiting the shannon expansion for the reduction of configuration memory.Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013FPGAA novel FPGA design framework with VLSI post-routing performance analysis (abstract only).Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013FPLDefect-robust FPGA architectures for intellectual property cores in system LSI.Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013FPLAn automatic FPGA design and implementation framework.Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012FCCMDesigning Flexible Reconfigurable Regions to Relocate Partial Bitstreams.Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012FPLFault detection and avoidance of FPGA in various granularities.Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012ICA3PPFault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration.Makoto Fujino, Hiroki Tanaka, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi
2012ICA3PPA Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration.Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2010FCCMImproving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration.Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2009FPLA novel states recovery technique for the TMR softcore processor.Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
1989ISCASIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture.Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita