| 2026 | ASPDAC | Analysis and Design of Oblong Coils and Standard-Cell-Based Receiver for Area-Efficient Edge-Coupled Inductive Coupling Transceiver. | Yuki Mitarai, Mototsugu Hamada, Atsutake Kosuge |
| 2025 | ASPDAC | A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor. | Yuxuan Pan, Dongzhu Li, Mototsugu Hamada, Atsutake Kosuge |
| 2025 | ISCAS | A 83.7% Resource Reduced FPGA-based Wired-Logic DNN Processor by Using Mixed-Precision Module Embedding Into Non-Linear Function LUT. | Yuxuan Pan, Mototsugu Hamada, Atsutake Kosuge |
| 2024 | ISCAS | Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions. | Dongzhu Li, Tianqi Zhao, Kenji Kobayashi, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
| 2023 | ASPDAC | A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network. | Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda |
| 2023 | ASPDAC | A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS. | Rei Sumikawa, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
| 2023 | ISCAS | A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network. | Dongzhu Li, Yao-Chung Hsu, Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
| 2023 | IECON | An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique. | Eitaro Kobayashi, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
| 2022 | ASPDAC | A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation. | Reiji Miura, Saito Shibata, Masahiro Usui, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
| 2021 | ASPDAC | Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface. | Tatsuo Omori, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda |
| 2021 | ASPDAC | A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS. | Kota Shiba, Tatsuo Omori, Mototsugu Hamada, Tadahiro Kuroda |
| 2020 | ISCAS | A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. | Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda |
| 2019 | ISCAS | Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming. | Tomoya Arakawa, Joshin Sone, Mitsuji Okada, Mototsugu Hamada, Tadahiro Kuroda |
| 2018 | ISCAS | Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers. | Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda |
| 2009 | ASPDAC | RF-analog circuit design in scaled SoC. | Nobuyuki Itoh, Mototsugu Hamada |
| 2007 | ICCD | An automated runtime power-gating scheme. | Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki |
| 1998 | DAC | Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. | Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda |