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Mudit Bhargava

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

11

Venues

10

Active years

2009–2026

Best venue rank

A*

Where they publish

Papers

11 indexed papers, newest first.

YearVenueTitleAuthors
2026AsiaCCSSCREAM: Secure Channels for Real-time Evaluation of Additive Manufacturing.Prithwish Basu Roy, Jason Blocklove, Mudit Bhargava, Hammond Pearce, Prashanth Krishnamurthy, Ozgur Sinanoglu, Nikhil Gupta, Farshad Khorrami, Ramesh Karri
2025ICCADInvited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D Integration.Gauthaman Murali, Mudit Bhargava, Shairfe Salahuddin, Zhichao Chen, Archana Pandey, Srivatsa Rangachar Srinivasa, Prerna Budhkar, Ragh Kuttappa, Vinayak Honkote, Prashanth Sakthi, Myung-Hee Na, Tanay Karnik
2019DACOn-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators.Haitong Li, Mudit Bhargava, Paul N. Whatmough, H.-S. Philip Wong
2019ISLPEDEnhanced 3D Implementation of an ArmXiaoqing Xu, Mudit Bhargava, Steve Moore, Saurabh Sinha, Brian Cline
2014DATEAn efficient reliable PUF-based cryptographic key generator in 65nm CMOS.Mudit Bhargava, Ken Mai
2013CHESA High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement.Mudit Bhargava, Ken Mai
2013ITCSCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states.Ben Niewenhuis, Ronald D. Blanton, Mudit Bhargava, Ken Mai
2013PRDCBuilding Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC.Jangwoo Kim, Hyunggyun Yang, Mark P. McCartney, Mudit Bhargava, Ken Mai, Babak Falsafi
2011FPGAFPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only).Yu Cai, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai
2010DACVirtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun
2009ICCDA Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes.Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun