Muralidaran Vijayaraghavan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
14
Venues
5
Active years
2007–2018
Best venue rank
A*
Where they publish
Papers
14 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | ISCA | Constructing a Weak Memory Model. | Sizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright, Mehdi Alipour, Arvind |
| 2015 | CAV | Modular Deductive Verification of Multiprocessor Hardware Designs. | Muralidaran Vijayaraghavan, Adam Chlipala, Arvind, Nirav Dave |
| 2014 | MEMOCODE | A new synthesis procedure for atomic rules containing multi-cycle function blocks. | Michal Karczmarek, Arvind, Muralidaran Vijayaraghavan |
| 2013 | MEMOCODE | Modular compilation of guarded atomic actions. | Muralidaran Vijayaraghavan, Nirav Dave, Arvind |
| 2012 | ISPASS | Fast and cycle-accurate modeling of a multicore processor. | Asif Khan, Muralidaran Vijayaraghavan, Silas Boyd-Wickizer, Arvind |
| 2012 | MEMOCODE | A general technique for deterministic model-cycle-level debugging. | Asif Khan, Muralidaran Vijayaraghavan, Arvind |
| 2010 | MEMOCODE | Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). | Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer |
| 2009 | MEMOCODE | Implementing a fast cartesian-polar matrix interpolator. | Abhinav Agarwal, Nirav Dave, Kermin Fleming, Asif Khan, Myron King, Man Cheuk Ng, Muralidaran Vijayaraghavan |
| 2009 | MEMOCODE | Bounded Dataflow Networks and Latency-Insensitive circuits. | Muralidaran Vijayaraghavan, Arvind |
| 2008 | FPGA | A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer |
| 2008 | ISPASS | Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer |
| 2008 | MEMOCODE | High-throughput Pipelined Mergesort. | Kermin Fleming, Myron King, Man Cheuk Ng, Asif Khan, Muralidaran Vijayaraghavan |
| 2007 | MEMOCODE | Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. | Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan |
| 2007 | MEMOCODE | From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols. | Man Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks |