Nagaraj Ns
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
1999–2010
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | DAC | What's cool for the future of ultra low power designs? | Nagaraj Ns, John Byler, Koorosh Nazifi, Venugopal Puvvada, Toshiyuki Saito, Alan Gibbons, S. Balajee |
| 2010 | DAC | Who solves the variability problem? | Nagaraj Ns, Juan C. Rey, Jamil Kawa, Robert C. Aitken, Christian Ltkemeyer, Vijay Pitchumani, Andrzej J. Strojwas, Steve Trimberger |
| 2001 | VLSID | Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. | Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell |
| 1999 | DATE | Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. | Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano |
| 1999 | ICCD | Performance and Reliability Verification of C6201/C6701 Digital Signal Processors. | Nagaraj Ns, Frank Cano, Sudha Thiruvengadam, Deepak Kapoor |
| 1999 | VLSID | Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis. | Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell |