Nagendra Dwarakanath Gulur
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2012–2014
Best venue rank
A*
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | MICRO | Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. | Nagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan |
| 2012 | ICS | Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. | Nagendra Dwarakanath Gulur, R. Manikantan, Mahesh Mehendale, R. Govindarajan |