Najmi T. Jarwala
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
2
Active years
1989–1996
Best venue rank
A
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1996 | VTS | Hardware-Software Co-Design for Test: It's the Last Straw! | J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard |
| 1995 | ITC | A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus. | Wuudiann Ke, Duy Le, Najmi T. Jarwala |
| 1994 | ITC | Designing "Dual-Personality" IEEE 1149.1-Compliant Multi-Chip Modules. | Najmi T. Jarwala |
| 1992 | ITC | A Framework for Boundary-Scan Based System Test Diagnosis. | Najmi T. Jarwala, Paul Stiling, Enn Tammaru, Chi W. Yau |
| 1991 | ITC | Achieving Board-Level BIST Using the Boundary-Scan Master. | Najmi T. Jarwala, Chi W. Yau |
| 1990 | ITC | The boundary-scan master: target applications and functional requirements. | Chi W. Yau, Najmi T. Jarwala |
| 1989 | ITC | A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects. | Najmi T. Jarwala, Chi W. Yau |
| 1989 | ITC | A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects. | Najmi T. Jarwala, Chi W. Yau |