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Nan-Chi Chou

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

11

Venues

4

Active years

1992–2009

Best venue rank

A*

Where they publish

Papers

11 indexed papers, newest first.

YearVenueTitleAuthors
2009DACLow power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng
2005ASPDACA practical cut-based physical retiming algorithm for field programmable gate arrays.Peter Suaris, Dongsheng Wang, Nan-Chi Chou
2005FPGAThe effect of post-layout pin permutation on timing.Yuzheng Ding, Peter Suaris, Nan-Chi Chou
2005ICCADImproving the efficiency of static timing analysis with false paths.Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
2004FPGAFast adders in modern FPGAs.Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris
2004FPGAIncremental physical resynthesis for timing optimization.Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou
2003DACAn algebraic multigrid solver for analytical placement with layout based clustering.Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
2003FPGAA physical retiming algorithm for field programmable gate arrays.Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou
1994DACCircuit Partitioning for Huge Logic Emulation Systems.Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof
1993ICCADPerformance-driven partitioning using retiming and replication.Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku
1992ICCADAn optimal probe testing algorithm for the connectivity verification of MCM substrates.So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu