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Naoya Torii

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

10

Venues

8

Active years

1999–2016

Best venue rank

A*

Where they publish

Papers

10 indexed papers, newest first.

YearVenueTitleAuthors
2016CCSEvaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs.Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto
2014AINAA Spoofing Attack against a Cancelable Biometric Authentication Scheme.Tetsuya Izu, Yumi Sakemi, Masahiko Takenaka, Naoya Torii
2014FedCSISSecurity Evaluation of Bistable Ring PUFs on FPGAs using Differential and Linear Analysis.Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii
2014IWSECA Technique Using PUFs for Protecting Circuit Layout Designs against Reverse Engineering.Dai Yamamoto, Masahiko Takenaka, Kazuo Sakiyama, Naoya Torii
2013CARDISEvaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches.Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh, Naoya Torii
2002CHESDPA Countermeasures by Improving the Window Method.Kouichi Itoh, Jun Yajima, Masahiko Takenaka, Naoya Torii
2001FSEThe Block Cipher SC2000.Takeshi Shimoyama, Hitoshi Yanami, Kazuhiro Yokoyama, Masahiko Takenaka, Kouichi Itoh, Jun Yajima, Naoya Torii, Hidema Tanaka
2001ICISCDPA Countermeasure Based on the "Masking Method".Kouichi Itoh, Masahiko Takenaka, Naoya Torii
2000CHESImplementation of Elliptic Curve Cryptographic Coprocessor over GF(2Souichi Okada, Naoya Torii, Kouichi Itoh, Masahiko Takenaka
1999CHESFast Implementation of Public-Key Cryptography ona DSP TMS320C6201.Kouichi Itoh, Masahiko Takenaka, Naoya Torii, Syouji Temma, Yasushi Kurihara