Naran Sirisantana
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
4
Active years
2000–2003
Best venue rank
B
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2003 | ASPDAC | Integer linear programming-based synthesis of skewed logic circuits. | Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy |
| 2003 | DATE | Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. | Naran Sirisantana, Kaushik Roy |
| 2001 | ISLPED | Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. | Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy |
| 2000 | ICCD | High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. | Naran Sirisantana, Liqiong Wei, Kaushik Roy |