Navneet Gupta
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
3
Active years
2013–2019
Best venue rank
C
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | ISCAS | A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS. | B. Dinesh Kumar, Hitesh Shrimali, Navneet Gupta |
| 2019 | ISCAS | Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator. | Vijender Kumar Sharma, B. Dinesh Kumar, Muhammed Suhail Illikkal, Jai Narayan Tripathi, Navneet Gupta, Hitesh Shrimali |
| 2017 | DATE | Tunnel FET based refresh-free-DRAM. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2016 | DATE | 3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2016 | ISCAS | Ultra-compact SRAM design using TFETs for low power low voltage applications. | Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel |
| 2015 | ISCAS | Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications. | Navneet Gupta, Adam Makosiej, Oliver Thomas, Amara Amara, Andrei Vladimirescu, Costin Anghel |
| 2013 | VLSID | PODIA: Power Optimization through Differential Imbalanced Amplifier. | Prashant Dubey, Atul Kumar Kashyap, Navneet Gupta, Kaushik Saha |