Neeraj Kapoor
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2019–2019
Best venue rank
National
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | VLSID | Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler. | Vinay Kumar, Neeraj Kapoor, Sudhir Kumar, Monila Juneja, Amit Khanuja |