| 2008 | DAC | A "true" electrical cell model for timing, noise, and power grid verification. | Noel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin |
| 2007 | DAC | Comparative Analysis of Conventional and Statistical Design Techniques. | Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De |
| 2007 | ICCAD | A nonlinear cell macromodel for digital applications. | Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout |
| 2006 | DAC | A multi-port current source model for multiple-input switching effects in CMOS library cells. | Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout |
| 2005 | DAC | Statistical static timing analysis: how simple can we get? | Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail |
| 2004 | DAC | Statistical timing analysis based on a timing yield model. | Farid N. Najm, Noel Menezes |
| 2001 | VLSID | Optimization and Analysis Techniques for the Deep Submicron Regime. | Noel Menezes, Sachin S. Sapatnekar |
| 1999 | DAC | Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching. | Chung-Ping Chen, Noel Menezes |
| 1999 | VLSID | Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. | Noel Menezes, Chung-Ping Chen |
| 1997 | ICCD | Clustering and Load Balancing for Buffered Clock Tree Synthesis. | Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi |
| 1995 | DAC | Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. | Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi |
| 1995 | ICCAD | A sequential quadratic programming approach to concurrent gate and wire sizing. | Noel Menezes, Ross Baldick, Lawrence T. Pileggi |
| 1994 | DAC | A Gate-Delay Model for high-Speed CMOS Circuits. | Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage |
| 1994 | ICCAD | RC interconnect synthesis-a moment fitting approach. | Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage |
| 1993 | DAC | Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. | Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage |