Panu Sjovall
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2015–2017
Best venue rank
Multiconference
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | ICASSP | High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA. | Panu Sjovall, Vili Viitamki, Jarno Vanne, Timo D. Hmlinen |
| 2017 | ISCAS | High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA. | Vili Viitamki, Panu Sjovall, Jarno Vanne, Timo D. Hmlinen |
| 2015 | DSD | High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA. | Panu Sjovall, Janne Virtanen, Jarno Vanne, Timo D. Hmlinen |