Paras Garg
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
2
Active years
2024–2026
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | VLSID | A Partially Loop-Unrolled Noise-Shaping SAR ADC Achieving 57dB-SNDR in 40MHz-BW at 320MS/s in 18nm FD-SOI CMOS Technology. | Anamika Sharma, Luv Pandey, Paras Garg, Rajesh Zele |
| 2025 | ISCAS | Three-Level Output Side Gate Driver for 1 V Thin-Gate-Oxide NMOSFET Switch in a SIDO Converter. | Abhijit Keshri, Pramit Banerjee, Gautam Dey Kanungo, Kallol Chatterjee, Paras Garg, Santanu Kapat, Debashis Mandal |
| 2024 | ISCAS | Loop Filter Design Considerations for Noise-Shaping in SAR ADCs. | Anamika Sharma, Luv Pandey, Paras Garg, Rajesh Zele |
| 2024 | ISCAS | A Novel 2.7 pJ/bit, Low Supply, Power Efficient, Wide-Range 2.5-6 Gb/s Transmitter for 4-Channel High-Speed Serial Transmit Port (HSSTP) in 28nm FD-SOI Technology. | Sameer Vashishtha, Prashant Kumar Singh, Mohd. Rizvi, Paras Garg |