Paul Racunas
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
6
Active years
1997–2021
Best venue rank
A*
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | MICRO | Characterizing and Mitigating Soft Errors in GPU DRAM. | Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, Stephen W. Keckler |
| 2020 | ITC | On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors. | Richard Bramley, Yanxiang Huang, Guangshan Duan, Nirmal R. Saxena, Paul Racunas |
| 2019 | ITC | Resiliency of automotive object detection networks on GPU architectures. | Atieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang |
| 2018 | DSN | Low Overhead Tag Error Mitigation for GPU Architectures. | Atieh Lotfi, Nirmal R. Saxena, Richard Bramley, Paul Racunas, Philip P. Shirvani |
| 2015 | MICRO | A fast and accurate analytical technique to compute the AVF of sequential bits in a processor. | Steven Raasch, Arijit Biswas, Jon Stephan, Paul Racunas, Joel S. Emer |
| 2007 | HPCA | Perturbation-based Fault Screening. | Paul Racunas, Kypros Constantinides, Srilatha Manne, Shubhendu S. Mukherjee |
| 2005 | ISCA | Computing Architectural Vulnerability Factors for Address-Based Structures. | Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan |
| 2003 | ICS | Partitioned first-level cache design for clustered microarchitectures. | Paul Racunas, Yale N. Patt |
| 1997 | MICRO | Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. | Jared Stark, Paul Racunas, Yale N. Patt |