Pavel Bencek
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
5
Active years
2014–2019
Best venue rank
National
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | FCCM | Scalable P4 Deparser for Speeds Over 100 Gbps. | Jakub Cabal, Pavel Bencek, Jana Foltova, Juraj Holub |
| 2018 | FPGA | Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. | Jakub Cabal, Pavel Bencek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek |
| 2018 | ICNP | Verification of Generated RTL from P4 Source Code. | Radek Isa, Pavel Bencek, Viktor Pus |
| 2017 | FPL | Line rate programmable packet processing in 100Gb networks. | Pavel Bencek, Viktor Pus, Jan Korenek, Michal Kekely |
| 2016 | FCCM | P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers. | Pavel Bencek, Viktor Pus, Hana Kubtov |
| 2014 | DSD | Architecture of Effective High-Speed Network Stream Merger. | Pavel Bencek, Hana Kubtov, Viktor Pus |
| 2014 | FPGA | Application specific processor with high level synthesized instructions (abstract only). | Viktor Pus, Pavel Bencek |
| 2014 | FPL | Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. | Lukas Kekely, Viktor Pus, Pavel Bencek, Jan Korenek |