| 2025 | ARITH | Implementation Evaluation of Fixed-Point Multipliers for Complex Numbers. | Per Larsson-Edefors, Erik Brjeson |
| 2025 | ISCAS | Low-Power Complex Multiplier Pin Assignment Based on Spatial and Temporal Signal Properties. | Per Larsson-Edefors, Erik Brjeson |
| 2025 | ISCAS | FPGA-Based Wordlength Optimization for DSP. | Chenhao Yang, Jinsheng Bian, Erik Brjeson, Per Larsson-Edefors |
| 2016 | CASES | Redesigning a tagless access buffer to require minimal ISA changes. | Carlos Sanchez, Peter Gavin, Daniel Moreau, Magnus Sjlander, David B. Whalley, Per Larsson-Edefors, Sally A. McKee |
| 2016 | DATE | Practical way halting by speculatively accessing halt tags. | Daniel Moreau, Alen Bardizbanyan, Magnus Sjlander, David B. Whalley, Per Larsson-Edefors |
| 2015 | ICCD | Exploring early and late ALUs for single-issue in-order pipelines. | Alen Bardizbanyan, Per Larsson-Edefors |
| 2014 | DATE | Reducing set-associative L1 data cache energy by early load data dependence detection (ELD | Alen Bardizbanyan, Magnus Sjlander, David B. Whalley, Per Larsson-Edefors |
| 2013 | CGO | Improving data access efficiency by using a tagless access buffer (TAB). | Alen Bardizbanyan, Peter Gavin, David B. Whalley, Magnus Sjlander, Per Larsson-Edefors, Sally A. McKee, Per Stenstrm |
| 2013 | ICCD | Speculative tag access for reduced energy dissipation in set-associative L1 data caches. | Alen Bardizbanyan, Magnus Sjlander, David B. Whalley, Per Larsson-Edefors |
| 2013 | ISCAS | A SiGe 8-channel comparator for application in a synthetic aperture radiometer. | Erik Ryman, Stefan Back Andersson, J. Riesbeck, Slavko Dejanovic, Anders Emrich, Per Larsson-Edefors |
| 2012 | ISCAS | Feasibility study of FPGA-based equalizer for 112-Gbit/s optical fiber receivers. | Fredrik Toft, Niclas Rousk, Jonas Mrtensson, Marco Forzati, Bengt-Erik Olsson, Per Larsson-Edefors |
| 2010 | DSD | Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. | Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors |
| 2007 | DSD | High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. | Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis |
| 2006 | ISCAS | Multiplier reduction tree with logarithmic logic depth and regular connectivity. | Henrik Eriksson, Per Larsson-Edefors, Mary Sheeran, Magnus Sjlander, Daniel Johansson, Martin Scholin |
| 2005 | ISCAS | A low-leakage twin-precision multiplier using reconfigurable power gating. | Magnus Sjlander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson |
| 2004 | ICCD | An Efficient Twin-Precision Multiplier. | Magnus Sjlander, Henrik Eriksson, Per Larsson-Edefors |
| 2004 | ISCAS | Evaluation of power cut-off techniques in the presence of gate leakage. | Mindaugas Drazdziulis, Per Larsson-Edefors |
| 2004 | ISCAS | Glitch-conscious low-power design of arithmetic circuits. | Henrik Eriksson, Per Larsson-Edefors |
| 2004 | ISCAS | Dynamic pass-transistor dot operators for efficient parallel-prefix adders. | Henrik Eriksson, Per Larsson-Edefors |
| 2004 | VLSID | On Maximum Current Estimation in CMOS Digital Circuits. | Dainius Ciuplys, Per Larsson-Edefors |
| 2003 | ASPDAC | A deep submicron power estimation methodology adaptable to variations between power characterization and estimation. | Daniel Eckerbert, Per Larsson-Edefors |
| 2003 | ASPDAC | Full-custom vs. standard-cell design flow: an adder case study. | Henrik Eriksson, Per Larsson-Edefors, Tomas Henriksson, Christer Svensson |
| 2003 | ICCD | A Mixed-Mode Delay-Locked-Loop Architecture. | Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors |
| 2001 | DSD | Interconnect-Driven Short-Circuit Power Modeling. | Daniel Eckerbert, Per Larsson-Edefors |
| 2001 | ISCAS | Cycle-true leakage current modeling for CMOS gates. | Daniel Eckerbert, Per Larsson-Edefors |
| 2001 | ISCAS | A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder. | Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour |
| 2001 | ISCAS | A regular parallel multiplier which utilizes multiple carry-propagate adders. | Henrik Eriksson, Per Larsson-Edefors, William P. Marnane |
| 2000 | ISCAS | GLMC: interconnect length estimation by growth-limited multifold clustering. | Atila Alvandpour, Per Larsson-Edefors, Christer Svensson |
| 2000 | ISCAS | An interconnect-driven design of a DFT processor. | Daniel Eckerbert, Henrik Eriksson, Per Larsson-Edefors, Anders Edman |
| 1998 | ISLPED | Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. | Atila Alvandpour, Per Larsson-Edefors, Christer Svensson |