| 2011 | ITC | Transition test bring-up and diagnosis on UltraSPARC | Liang-Chi Chen, Peter Dahlgren, Paul Dickinson, Scott Davidson |
| 2009 | ITC | Using transition test to understand timing behavior of logic circuits on UltraSPARC | Liang-Chi Chen, Paul Dickinson, Peter Dahlgren, Scott Davidson, Olivier Caty, Kevin Wu |
| 2008 | ITC | Transition Test on UltraSPARC- T2 Microprocessor. | Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen |
| 2005 | ITC | Microprocessor silicon debug based on failure propagation tracing. | Olivier Caty, Peter Dahlgren, Ismet Bayraktaroglu |
| 2003 | ITC | Latch Divergency In Microprocessor Failure Analysis. | Peter Dahlgren, Paul Dickinson, Ishwar Parulkar |
| 1998 | ITC | Switch-level bridging fault simulation in the presence of feedbacks. | Peter Dahlgren |
| 1997 | VTS | Switch-level modeling of feedback faults using global oscillation control. | Peter Dahlgren |
| 1996 | DAC | Oscillation Control in Logic Simulation using Dynamic Dominance Grahps. | Peter Dahlgren |
| 1996 | VTS | A fault model for switch-level simulation of gate-to-drain shorts. | Peter Dahlgren, Peter Lidn |
| 1995 | ICCAD | A multiple-dominance switch-level model for simulation of short faults. | Peter Dahlgren |
| 1995 | ISCAS | Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS Checkers. | Peter Lidn, Peter Dahlgren |
| 1995 | VTS | Switch-level modeling of transistor-level stuck-at faults. | Peter Lidn, Peter Dahlgren |
| 1994 | DAC | Modeling of Intermediate Node States in switch-Level Networks. | Peter Dahlgren, Peter Lidn |
| 1993 | ICCAD | Efficient modeling of switch-level networks containing undetermined logic node states. | Peter Dahlgren, Peter Lidn |
| 1992 | ITC | Transistor Fault Coverage for Self-Testing CMOS Checkers. | Peter Lidn, Peter Dahlgren, Jan Torin |